LTC1861 LINER [Linear Technology], LTC1861 Datasheet - Page 8

• Manufacturer Part Number: LTC1861
• Description: mPower, 12-Bit, 250ksps 1- and 2-Channel ADCs in MSOP
• Manufacturer: LINER [Linear Technology]

LTC1860/LTC1861
TEST CIRCUITS
APPLICATIO S I FOR ATIO
8
LTC1860 OPERATION
Operating Sequence
The LTC1860 conversion cycle begins with the rising edge
of CONV. After a period equal to t
finished. If CONV is left high after this time, the LTC1860
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1860 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefinitely. See Figure 1.
Voltage Waveforms for SDO Delay Times, t
SDO
SCK
CONV
SDO
SDO
Load Circuit for t
TEST POINT
t
V
hDO
IL
Voltage Waveforms for t
U
20pF
3k
t
dDO
U
dDO
, t
r
t
, t
en
CONV
f
, t
W
V
t
dis
CC
dis
WAVEFORM 1
t
dis
en
, the conversion is
and t
WAVEFORM 2, t
dDO
en
1860 TC02
and t
1860 TC03
1860 TC01
U
V
V
hDO
OH
OL
en
Analog Inputs
The LTC1860 has a unipolar differential analog input. The
converter will measure the voltage between the “IN
“IN
equals zero. Full scale occurs when IN
V
“IN
mode noise on the inputs is rejected by the ADC. If “IN
is grounded and V
will result on “IN
Reference Input
The voltage on the reference input of the LTC1860 (and the
LTC1861 MSOP package) defines the full-scale range of
the A/D converter. These ADCs can operate with reference
voltages from V
WAVEFORM 1
WAVEFORM 2
(SEE NOTE 1)
(SEE NOTE 2)
REF
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
–
–
SDO
” inputs. A zero code will occur when IN
” inputs are sampled at the same time, so common
Voltage Waveforms for SDO Rise and Fall Times, t
minus 1LSB. See Figure 2. Both the “IN
CONV
SDO
SDO
t
r
CC
Voltage Waveforms for t
+
REF
” as shown in Figure 3.
to 1V.
is tied to V
CC
, a rail-to-rail input span
t
dis
dis
+
minus IN
t
f
V
IH
+
minus IN
1860 TC04
–
10%
90%
r
, t
+
equals
V
V
+
” and
1860 TC05
OH
OL
f
” and
18601f
–
–
”