LTC1661C LINER [Linear Technology], LTC1661C Datasheet - Page 6

• Manufacturer Part Number: LTC1661C
• Description: Micropower Dual 10-Bit DAC in MSOP
• Manufacturer: LINER [Linear Technology]

LTC1661
PIN
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on D
into the register. When CS/LD is pulled high, SCK is
disabled and the operation(s) specified in the Control
code, A3-A0, is (are) performed. CMOS and TTL compat-
ible.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
D
the D
edge of SCK. CMOS and TTL compatible.
DEFINITIONS
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
Where V
two adjacent codes.
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
than zero. The INL error at a given input code is calculated
as follows:
6
IN
DNL = ( V
U
(Pin 3): Serial Interface Data Input. Input word data on
IN
FUNCTIONS
U
pin is shifted into the 16-bit register on the rising
OUT
U
OUT
is the measured voltage difference between
U
– LSB)/LSB
U
IN
REF (Pin 4): Reference Voltage Input. 0V V
V
The output range is
V
GND (Pin 7): System Ground.
Where V
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
Resolution (n): Defines the number of DAC output states
(2
imply linearity.
Voltage Offset Error (V
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
OUT A
CC
n
INL = [V
LSB = V
0
) that divide the full-scale range. Resolution does not
(Pin 6): Supply Voltage Input. 2.7V V
, V
V
OUTA
OUT
OUT B
REF
OUT
is the output voltage of the DAC measured at
,
/1024
V
(Pins 8,5): DAC Analog Voltage Outputs.
OUTB
– V
OS
– (V
V
OS
REF
): Nominally, the voltage at the
FS
– V
1023
1024
OS
)(code/1023)]/LSB
CC
REF
5.5V.
V
CC
.