C505-2RM SIEMENS [Siemens Semiconductor Group], C505-2RM Datasheet
C505-2RM
Related parts for C505-2RM
C505-2RM Summary of contents
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... Microcomputer Components 8-Bit CMOS Microcontroller C505 C505C/C505A C505CA Data Sheet 12.97 ...
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Edition 12.97 Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for ...
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... C505 / C505C: 256 Byte 256 Byte C505A / C505CA: 1 KByte Timer C500 0 8-Bit Core USART Timer 8 Datapointers 1 Program Memory C505 / C505C ROM C505A / C505CA OTP 3 C505C C505A C505CA Port 0 8 Analog Inputs / Port 1 8 Digit Port ...
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... Pin configuration is compatible to C501, C504, C511/C513-family • Temperature ranges: SAB-C505 versions SAF-C505 versions SAH-C505 versions SAK-C505 versions Table 1 Differences in Functionality of the C505 MCUs Device Internal Program Memory XRAM Size ROM C505-2RM 16 KB C505-LM – C505C-2RM 16 KB C505C-LM – C505A-4EM – C505CA-4EM – ...
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... Table 2 Ordering Information Type Ordering Code Package SAB-C505-2RM Q67127-DXXXX SAB-C505-LM Q67127-C2057 SAF-C505-2RM Q67127-DXXXX SAF-C505-LM Q67127-C2056 SAB-C505C-2RM Q67127-DXXXX SAB-C505C-LM Q67127-C2029 SAF-C505C-2RM Q67127-DXXXX SAF-C505C-LM Q67127-C2030 SAB-C505A-4EM Q67127-C2060 SAF-C505A-4EM Q67127-C2061 SAB-C505CA-4EM Q67127-C1082 SAB-C505CA-4EM Q67127-C2058 Note: The ordering number of the ROM types (DXXXX extension) is defined after program release (verification) of the customer. Versions for the extended temperature range – ...
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... EA ALE PSEN Figure 2 Logic Symbol Additional Literature For further information about the C505/C505C/C505A/C505CA the following literature is available: Title C505 8-Bit CMOS Microcontroller User’s Manual C500 Microcontroller Family Architecture and Instruction Set User’s Manual C500 Microcontroller Family - Pocket Guide Semiconductor Group ...
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... V AREF V AGND P1.0 / AN0 / INT3 / CC0 P1.1 / AN1 / INT4 / CC1 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 / INT6 / CC3 P1.4 / AN4 This pin functionality is not available in the C505 and C505A. Figure 3 C505 Pin Configuration P-MQFP-44 Package (top view) Semiconductor Group ...
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... P1.2 / AN2 / INT5 / CC2 Analog input channel 2 / P1.3 / AN3 / INT6 / CC3 Analog input channel 3 P1.4 / AN4 P1.5 / AN5 / T2EX P1.6 / AN6 / CLKOUT P1.7 / AN7 / T2 Port 1 is used for the low-order address byte during program verification of the C505-2R and C505C-2R. 8 C505 / C505C C505A / C505CA interrupt 3 input / capture/compare channel 0 I/O interrupt 4 input / ...
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... External interrupt 1 input / timer 1 gate control input P3 Timer 0 counter input P3 Timer 1 counter input P3 control output; latches the data byte from port 0 into the external data memory P3 control output; enables the external data memory 9 C505 / C505C C505A / C505CA the DC IL 1997-12-01 ...
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... The output latch corresponding to the secondary function RXDC must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the two pins of port 4 as follows (C505C and C505CA only) : P4.0 / TXDC Transmitter output of CAN controller P4.1 / RXDC ...
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... When instructions are executed from internal ROM or OTP (EA=1) the ALE generation can be disabled by bit EALE in SFR SYSCON. ALE should not be driven during reset operation. 11 C505 / C505C C505A / C505CA the DC characteristics) IL 1997-12-01 ...
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... H (C505 and C505C) or less than 8000H (C505A and C505CA). When held at low level, the C505 fetches all instructions from external program memory. EA should not be driven during reset operation. For the C505-L and the C505C-L this pin must be tied low. I/O Port 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1’ ...
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... Semiconductor Group XRAM 1) RAM 256 Byte 256 Byte 1 KByte 1) MUX 1) C505 / C505C: 256B XRAM / 16KB ROM / 8-Bit ADC C505A / C505CA: 1KB XRAM / 32KB OTP / 10-Bit ADC 13 C505 / C505C C505A / C505CA ROM OTP KByte Port 0 Port 0 8-Bit Digit Port 1 8-Bit Digit ...
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... CPU The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting one-byte two-byte, and 15% three- byte instructions. With a 16 MHz crystal, 58% of the instructions are executed in 375 ns. ...
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... Memory Organization The C505 CPU manipulates operands in the following four address spaces: – On-chip program memory : – Totally Kbyte internal/external program memory – Kbyte of external data memory – 256 bytes of internal data memory – Internal XRAM data memory : 256 byte (C505/C505C) – ...
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... Figure 6 shows the possible reset circuitries RESET Figure 6 Reset Circuitries Semiconductor Group C505 C505C C505A C505CA C505 C505C + C505A C505CA RESET 16 C505 / C505C C505A / C505CA V to allow a power-up reset with applied by connecting CC b) C505 C505C C505A C505CA & RESET MCS03633 1997-12-01 ...
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... Figure 7 shows the recommended oscillator circuits for crystal and external clock operation. External Clock Signal Figure 7 Recommended Oscillator Circuitries Semiconductor Group C XTAL2 MHz C505CA C XTAL1 for crystal operation V CC XTAL2 N.C. C505CA XTAL1 17 C505 / C505C C505A / C505CA C505 C505C C505A C505 C505C C505A MCS03634 1997-12-01 ...
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... Multiple Datapointers As a functional enhancement to the standard 8051 architecture, the C505 contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in the special function regsiter DPSEL. Figure 8 illustrates the datapointer addressing mechanism. ...
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... Semiconductor Group which requires embedded logic in the C500 allows the C500 to Emulation Hardware RESET RSYSCON EA RPCON ALE RTCON PSEN Port 0 Port 2 RPort 2 Target System Interface 19 C505 / C505C C505A / C505CA ICE-System Interface EH-IC Enhanced Hooks Interface Circuit RPort 0 TEA TALE TPSEN MCS02647 1997-12-01 ...
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... CPU and the other on-chip peripherals. The SFRs of the C505 are listed in table 4 and table 5. In table 4 they are organized in groups which refer to the functional blocks of the C505. The CAN-SFRs (applicable for the C505C and C505CA only) are also included in table 4 ...
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... This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The content of this SFR varies with the actual step of the C505 (eg C505 / C505A only 7) ...
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... C505 / C505C C505A / C505CA Reset XXXXXX11 B 00X00000 XXXXXX11 ...
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... F70B H F70C H F70D H F70E H F70F H F7n0 H F7n1 H F7n2 H F7n3 H F7n4 H F7n5 H F7n6 H F7n7 H F7n8 H F7n9 H F7nA H F7nB H F7nC H F7nD H F7nE H 23 C505 / C505C C505A / C505CA Reset 0UUUUUUU UUU11111 ...
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... SM0 SM1 SM2 REN . WDT ET2 ES OWDS WDTS . C505 / C505C C505A / C505CA Bit 3 Bit 2 Bit 1 Bit GF1 GF0 PDE IDLE ...
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... PSW ADCON0 00X0- 0000 ADDAT means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) C505 / C505A only 4) C505C / C505CA only Semiconductor Group Bit 7 Bit 6 Bit 5 Bit – – EALE RMAP CMOD – ...
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... Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers 5) The content of this SFR varies with the actual of the step C505 (eg C505 / C505C only 7) C505A / C505CA only Semiconductor Group ...
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... BOFF EWRN – RXOK TXOK LEC2 SJW 0 TSEG2 ID20-18 1 ID4-0 ID20-18 ID4-0 MSGVAL TXIE RMTPND TXRQ ID20-18 ID4-0 DLC 27 C505 / C505C C505A / C505CA Bit 3 Bit 2 Bit 1 EIE SIE IE LEC1 INTID BRP TSEG1 ID28- ID28-21 ID20-13 ID12 ID28-21 ID17-13 ...
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... Bit C505 / C505C C505A / C505CA Bit 3 Bit 2 Bit 1 Bit ...
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... I/O Ports The C505 has four 8-bit I/O ports and one 2-bit I/O port. Port open-drain bidirectional I/O port, while ports are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports will be pulled high and will source current when externally pulled low ...
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... External inputs INT0 and INT1 (P3.2, P3.3) can be OSC ÷ 6 OSC C C TR0 & =1 TR1 _ < C505 / C505C C505A / C505CA Input Clock internal external (max /6x32 /12x32 OSC OSC /12 OSC OSC f /6 OSC Timer 0/1 Input Clock ...
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... Timer/Counter 2 with Compare/Capture/Reload The timer 2 of the C505 provides additional compare/capture/reload features. which allow the selection of the following operating modes: – Compare : PWM signals with 16-bit/300 ns resolution (@ 20 MHz clock) – Capture : high speed capture inputs with 300 ns resolution – Reload ...
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... CRC register, which is preset by software. In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon- ding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been set. Semiconductor Group 32 C505 / C505C C505A / C505CA 1997-12-01 ...
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... Bit Comparator Compare 16 Bit Match Timer Register Timer Timer Circuit Overflow Figure 12 Port Latch in Compare Mode 0 Semiconductor Group Port Circuit S Internal D Bus Latch Write to CLK Latch R 33 C505 / C505C C505A / C505CA Read Latch Port Port Pin Q Read Pin MCS02661 1997-12-01 ...
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... Semiconductor Group Port Circuit Read Latch Internal D Bus Shadow Latch Write to CLK Latch a positive or negative transition at the corresponding pin, depending on the status of the bit I3FR in SFR T2CON. 34 C505 / C505C C505A / C505CA Port Latch CLK Q Read Pin MCS02662 1997-12-01 Port Pin ...
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... UART, variable baud rate 10 bits are transmitted (through received ( 9-bit UART, fixed baud rate 11 bits are transmitted (through received ( 9-bit UART, variable baud rate Like mode 2 35 C505 / C505C C505A / C505CA refers to the oscillator OSC 1997-12-01 ...
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... SMOD f – OSC X Controlled by timer 1 overflow : (2 SMOD X Controlled by baud rate generator (2 SMOD (32 baud rate generator overflow rate OSC OSC 36 C505 / C505C C505A / C505CA PCON.7 (SMOD) ÷ timer 1 overflow rate OSC Baud Rate Clock MCS02733 1997-12-01 ...
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... CAN Controller (C505C and C505CA only) The on-chip CAN controller, compliant to version 2.0B, is the functional heart which provides all resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the CPU of as much overhead as possible when controlling many different message objects (up to 15) ...
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... Each of these objects has a unique identifier and its own set of control and status bits. After the initial configuration, the Intelligent Memory can handle the reception and transmission of data without further microcontroller actions. Semiconductor Group 38 C505 / C505C C505A / C505CA 1997-12-01 ...
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... CAN > 10 MHz OSC CMOD BRP (SYSCON.3) (BTR0.0-5) f CAN 8 1 000000 000000 B 8 000000 B 39 C505 / C505C C505A / C505CA f is over 10 MHz (bit CMOD =0) osc MHz (bit CMOD=1) osc Full-CAN Module MCS03296 CAN Baudrate (Mbaud/sec) 1 0.5 1 1997-12-01 ...
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... A/D Converter (C505 and C505C only) The C505/C505C includes a high performance / high speed 8-bit A/D converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and provides the following features: – 8 multiplexed input channels (port 1), which can also be used as digital outputs/inputs – ...
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... IEX6 IEX5 IEX4 EAN5 EAN4 EAN3 EAN2 BSY ADM Single / Continuous Mode S&H Conversion Clock f ADC Input Clock C505 / C505C C505A / C505CA Internal Bus EX3 ECAN EADC IEX3 SWI IADC EAN1 EAN0 MX2 MX1 MX0 MX0 MX2 MX1 ADDAT ADST ...
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... A/D Converter (C505A and C505CA only) The C505 includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D converter provides the following features: – ...
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... EX4 IEX6 IEX5 IEX4 EAN5 EAN4 EAN3 BSY ADM Single / Continuous Mode S&H Conversion Clock f ADC Input Clock C505 / C505C C505A / C505CA Internal EADC EX3 ECAN IADC IEX3 SWI EAN2 EAN1 EAN0 MX2 MX1 MX0 MX2 MX1 MX0 ADDAT ADST ...
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... The C505 provides 12 interrupt vectors with four priority levels. Five interrupt requests can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter). One interrupt can be generated by the CAN controller (C505C and C505CA only software setting and in this case the interrupt vector is the same. Six interrupts may be triggered externally (P3.2/ INT0, P3 ...
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... Message Receive RXIE MCR0 Bit addressable Request flag is cleared by hardware Figure 21 Interrupt Structure, Overview Part 1 Note: Each of the 15 CAN controller message objects (C505C and C505CA only), shown in the shaded area of Figure 21 provides the bits/flags. Semiconductor Group IE0 0003 H TCON.1 EX0 IEN0.0 ...
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... EX1 IEN0.2 IEX3 0053 H EX3 IRCON.2 IEN1.2 IP1.2 TF1 001B H TCON.7 ET1 IEN0.3 IEX4 005B H IRCON.3 EX4 IEN1.3 EA IP1.3 IEN0.7 46 C505 / C505C C505A / C505CA Highest Priority Level Lowest Priority Level IP0 IP0.3 MCB03304 1997-12-01 ...
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... Semiconductor Group >1 0023 H ES IEN0.4 IEX5 0063 H IRCON.4 EX5 IEN1.4 IP1.4 >1 002B H ET2 IEN0.5 IEX6 006B H EX6 IRCON.5 IEN1.5 EA IP1.5 IEN0.7 47 C505 / C505C C505A / C505CA Highest Priority Level Lowest Priority Level IP0 IP0.5 MCB03305 1997-12-01 ...
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... The watchdog timer in the C505 is a 15-bit timer, which is incremented by a count rate of upto f /192 ...
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... RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts program execution by processing a power down interrupt after a final delay of typ order to allow the on-chip oscillator to stabilize. Semiconductor Group 49 C505 / C505C C505A / C505CA 1997-12-01 ...
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... Oscillator Figure 25 Functional Block Diagram of the Oscillator Watchdog Semiconductor Group Power - Down Mode Activated Control Logic < Frequency Delay Comparator f 2 OWDS 50 C505 / C505C C505A / C505CA Power-Down Mode Wake - Up Interrupt Internal Reset >1 IP0 ( Int. Clock MCB03308 1997-12-01 ...
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... Idle mode In the idle mode the main oscillator of the C505 continues to run, but the CPU is gated off from the clock signal. All peripheral units are further provided with the clock. The CPU status is preserved in its entirety ...
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... C505A/C505CA fast programming cycles are achieved (1 byte in 100 sec). Also several levels of OTP memory protection can be selected. For programming of the device, the C505A/C505CA must be put into the programming mode. This typically is done not in-system but in a special programming hardware. In the programming mode the C505A/C505CA operates as a slave device similar as an EPROM standalone memory device and must be controlled with address/data information, control lines, and an external 11 ...
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... Pin Configuration in Programming Mode N.C. N.C. N.C. N.C. N.C. N.C. N.C. Figure 27 P-MQFP-44 Pin Configuration of the C505A/C505CA in Programming Mode (Top View) Semiconductor Group C505A 39 C505CA C505 / C505C C505A / C505CA A12 ...
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... The following table 12 contains the functional description of all C505A/C505CA pins which are required for OTP memory programming. Table 12 Pin Definitions and Functions in Programming Mode Symbol Pin Number I/O RESET 4 PMSEL0 5 PMSEL1 7 PSEL 8 PRD 9 PALE 10 XTAL2 14 XTAL1 Input O = Output ...
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... EA I/O Data lines 0-7 During programming mode, data bytes are transferred via the bidirectional port 0 data lines. – Not Connected These pins should not be connected in programming mode. 55 C505 / C505C C505A / C505CA ) voltage level during PP high level. IH 1997-12-01 ...
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... During this period signals are not actively driven Figure 28 Basic Programming Mode Selection Semiconductor Group Stable "1" "0" 0,1 "0" "1" "0" Ready for access mode selection 56 C505 / C505C C505A / C505CA MCS03639 1997-12-01 ...
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... Read OTP lock bits Read OTP version byte Lock Bits Programming / Read The C505A/C505CA has two programmable lock bits which, when programmed according table 14, provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can also be read. ...
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... Voltage on pins with respect to ground ( CC absolute maximum ratings. Semiconductor Group T ) ......................................................... – 125 ....................................... – ......................................... – 0 must not exceed the values defined by the SS 58 C505 / C505C C505A / C505CA V +0 > < the 1997-12-01 ...
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... CC V – – OL1 V 2 2.4 OH2 V 0 – – – – – 10 C505 / C505C C505A / C505CA Unit Test Condition max. V 0.2 - 0.1 V – 0.2 - 0.3 V – 0.2 + 0.1 V – 0.5 V – 0.5 V – 0.5 V – 0. ...
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... I 20 MHz 28 MHz I 9 MHz 14 MHz 3 MHz I 4 MHz 3 MHz 3 C505 / C505C C505A / C505CA Unit Test Condition max. 13) 7) TBD mA TBD 8) TBD mA TBD 9) TBD mA TBD 10) TBD mA TBD TBD 2..5 TBD mA TBD 8) TBD ...
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... The absolute sum of input currents on all port pins may not exceed 50 mA. 4) Not 100% tested, guaranteed by design characterization. 5) Only valid for C505A and C505CA. 6) Only valid for C505A and C505CA in programming mode (active mode) is measured with: ...
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... CC max typ Figure 29 ICC Diagram of C505 and C505C C505/C505C: Power Supply Current Calculation Formulas Parameter Symbol Active mode I CC typ I CC max I Idle mode CC typ I CC max I Active mode with CC typ I slow-down enabled CC max Idle mode with ...
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... CC max typ Figure 30 ICC Diagram of C505A and C505CA C505A : Power Supply Current Calculation Formulas Parameter Symbol Active mode I CC typ I CC max I Idle mode CC typ I CC max I Active mode with CC typ I slow-down enabled CC max Idle mode with ...
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... A/D Converter Characteristics of C505 and C505C 10%, – 15 0.1 V; AREF CC Parameter Symbol V Analog input voltage t Sample time t Conversion cycle time Total unadjusted error T Internal resistance of R reference voltage source R Internal resistance of analog source C ADC input capacitance Notes see next page. ...
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... The AIN t , changes of the analog input voltage have no effect on the conversion the time for determining the digital result. Values for the S T 125 C505 / C505C C505A / C505CA 0.1 V and V AREF AGND 1997-12-01 ...
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... A/D Converter Characteristics of C505A and C505CA 10%, – 15 0.1 V; AREF CC SS Parameter Symbol V Analog input voltage Sample time t t Conversion cycle time Total unadjusted error T R Internal resistance of reference voltage source Internal resistance of R analog source C ADC input capacitance Notes see next page ...
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... the time for determining the digital result and the time for the S t depend on programming and can be taken from the table on ADC 4 guaranteed by design characterization for all AGND CC 67 C505 / C505C C505A / C505CA 1997-12-01 ...
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... Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN *) Interfacing the C505 to devices with float times permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group for the SAB- versions ...
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... Freq MHz to 12 MHz min. CLP 83.3 TCL 20 H TCL – – 0.5 69 C505 / C505C C505A / C505CA Variable Clock 1/CLP = 2 MHz to 12 MHz min. max. 3 CLP - 70 – 3 CLP - 70 – CLP - 27 – – 5/2 CLP – – CLP - 20 – 4 CLP - 133 – ...
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... Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN *) Interfacing the C505 to devices with float times permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group for the SAB- versions ...
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... TCL QVWX t 163 – 3 CLP + QVWH TCL t 5 – TCL WHQX t – 0 – RLAZ 71 C505 / C505C C505A / C505CA Variable Clock 1/CLP= 2 MHz to 16 MHz max. – – – 2 CLP+ TCL - 50 Hmin – CLP - 12 4 CLP - 50 4 CLP + TCL -75 Hmin CLP TCL ...
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... Duty Cycle 0.4 to 0.6 min. max. 62.5 62.5 25 – – L – – 0.4 0.6 25 37.5 72 C505 / C505C C505A / C505CA Variable CPU Clock 1/CLP = MHz min. max. 62.5 500 25 CLP - TCL L 25 CLP - TCL H – 10 – CLP CLP CLP * DC CLP * DC min max 1997-12-01 ...
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... Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN *) Interfacing the C505 to devices with float times permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group for the SAB- versions ...
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... Freq MHz to 20 MHz min. CLP 50 TCL 15 H TCL – – 0.5 74 C505 / C505C C505A / C505CA Variable Clock 1/CLP = 2 MHz to 20 MHz min. max. 3 CLP - 30 – 3 CLP - 30 – CLP - 15 – – 5/2 CLP – – CLP - 12 – 4 CLP - 50 – ...
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... ALE PSEN Port 0 Port 2 Figure 31 Program Memory Read Cycle Semiconductor Group t LHLL t t AVLL PLPH t LLPL t LLIV t PLIV t AZPL t LLAX Instr.IN t AVIV A8 - A15 75 C505 / C505C C505A / C505CA t PXAV t PXIZ t PXIX A15 MCT00096 1997-12-01 ...
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... Ri or DPL t AVWL Port 2 Figure 32 Data Memory Read Cycle Semiconductor Group t LLDV t t LLWL RLRH t RLDV t LLAX2 t RLAZ Data IN t AVDV P2 A15 from DPH 76 C505 / C505C C505A / C505CA t WHLH t RHDZ t RHDX Instr. from PCL A15 from PCH MCT00097 1997-12-01 ...
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... Figure 34 External Clock Drive on XTAL1 Semiconductor Group t t LLWL WLWH t QVWX t LLAX2 t QVWH Data OUT P2 A15 from DPH H TCL L CLP 77 C505 / C505C C505A / C505CA t WHLH t WHQX Instr.IN from PCL A8 - A15 from PCH 0 0 0.1 CC MCT03310 MCT00098 1997-12-01 ...
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... AC Characteristics of Programming Mode (C505A and C505CA only 11 Parameter ALE pulse width PMSEL setup to ALE rising edge Address setup to ALE, PROG, or PRD falling edge Address hold after ALE, PROG, or PRD falling edge Address, data setup to PROG or PRD Address, data hold after PROG or PRD ...
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... PAW PALE t PMS PMSEL1,0 t A8-A14 Port 2 Port 0 PROG Notes: PRD must be high during a programming write cycle. Figure 35 Programming Code Byte - Write Cycle Timing Semiconductor Group PAS PAH t t PCS 79 C505 / C505C C505A / C505CA A0-A7 D0-D7 t PWH t PWW PCH MCT03642 1997-12-01 ...
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... PMS PMSEL1,0 t Port 2 Port 0 PRD Notes: PROG must be high during a programming read cycle. Figure 36 Verify Code Byte - Read Cycle Timing Semiconductor Group PAS PAH A8-A14 t PAD t PRD t t PCS 80 C505 / C505C C505A / C505CA A0-A7 t PDH D0-D7 t PDF t PWH t PRW PCH MCT03643 1997-12-01 ...
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... PCH PCS t PMH t PWW D0-7 t PCS t PRD t PMS t PRW PROG must be high during a programming read cycle. 81 C505 / C505C C505A / C505CA PDH PMS PRD PDF t PMH t PRW MCT03644 t PCH t PDH t PDF t PMH MCT03645 1997-12-01 ...
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... ROM/OTP Verification Characteristics for C505 ROM Verification Mode 1 (C505-2R and C505C-2R only) Parameter Address to valid data P1.0 - P1.7 P2.0 - P2.6 Port 0 Address: P1 Data: Figure 39 ROM Verification Mode 1 Semiconductor Group Symbol min. t – AVQV Address t AVQV Data OUT Inputs: P2.6, P2.7, PSEN = P2 A14 P0 C505 / C505C C505A / C505CA Limit Values max ...
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... ROM/OTP Verification Characteristics for C505 (cont’d) ROM/OTP Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency ALE Port 0 P3.5 Figure 40 ROM/OTP Verification Mode 2 Semiconductor Group Symbol min. t – AWD t – ...
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... V for a logic ’1’ and 0.45 V for a logic ’0’ for a logic ’1’ and V IHmin ILmax Timing Reference Points Driving from External Source XTAL2 N.C. External Oscillator Signal XTAL1 84 C505 / C505C C505A / C505CA MCT00039 for a logic ’0’ MCT00038 level occurs XTAL2 ...
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... P-MQFP-44-1 (SMD) (Plastic Metric Quad Flat Package) Figure 44 P-MQFP-44 Package Outline Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 85 C505 / C505C C505A / C505CA Dimensions in mm 1997-12-01 ...