C504 SIEMENS [Siemens Semiconductor Group], C504 Datasheet
C504
Available stocks
Related parts for C504
C504 Summary of contents
Page 1
... Microcomputer Components 8-Bit CMOS Microcontroller C504 Data Sheet 05.96 ...
Page 2
... C504 Revision History: Previous Version: Page Page Subjects (major changes since last revision) (in previous ( Version) Version) Edition 05.96 This edition was realized using the software system FrameMaker . Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1996. ...
Page 3
... CMOS Microcontroller Advance Information • Fully compatible to standard 8051 microcontroller • MHz operating frequency • ROM (C504-2R only, optional ROM protection) • 256 8 RAM • 256 8 XRAM • Four 8-bit ports, (2 ports with mixed analog/digital I/O capability) • Three 16-bit timers/counters (timer 2 with up/down counter feature) • ...
Page 4
... Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (24 MHz) SAB-C504-2R40M Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (40 MHz) Note: Versions for extended temperature ranges – 40 ˚C to 110 ˚C (SAH-C504) and – 40 ˚C to 125 ˚C (SAK-C504) are available on request. The ordering number of ROM types (DXXXX extensions) is defined after program release (verification) of the customer ...
Page 5
... Figure 1 Logic Symbol Semiconductor Group 5 C504 ...
Page 6
... Figure 2 Pin Configuration (top view) Semiconductor Group 6 C504 ...
Page 7
... SS V external capacitor to 7 Analog input channel 0 / input to counter 2 Analog input channel 1 / capture/reload trigger of timer 2 / up-down count Analog input channel 2 / input/output of capture/compare channel 0 output of capture/compare channel 0 Input/output of capture/compare channel 1 Output of capture/compare channel 1 Input/output of capture/compare channel 2 Output of capture/compare channel C504 ...
Page 8
... COINI register (if they are enabled by the bits in SFR TRCON). CTRAP is an input pin with an internal pullup resistor. For power saving reasons, the signal source which drives the CTRAP input should be at high or floating level during power-down mode. 8 C504 ...
Page 9
... It is activated every six oscillator periodes except during an external data memory access. When instructions are executed from internal ROM (EA=1) the ALE generation can be disabled by bit EALE in SFR SYSCON the DC characteris-tics) because C504 ...
Page 10
... External Access Enable When held at high level, instructions are fetched from the internal ROM (C504-2R only) when the PC is less than 4000 H .When held at low level, the C504 fetches all instructions from external program memory. For the C504-L this pin must be tied low. ...
Page 11
... Functional Description The C504 basic architecture is fully compatible to the standard 8051 microcontroller family. While maintaining all architectural and operational characteristics of the SAB 80C52 / C501, the C504 incorporates some enhancements such as on-chip XRAM, A/D converter, fail save mechanisms, and a versatile capture/compare unit. Figure 3 shows a block diagram of the C504. ...
Page 12
... CPU The C504 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting one-byte two-byte, and 15 % three- byte instructions. With a 12 MHz crystal the instructions are executed in 1 MHz: 500 ns, 40 MHz : 300 ns) ...
Page 13
... Figure 4 C504 Memory Map The XRAM in the C504 is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory the same instruction types (MOVX instructions) must be used for accessing the XRAM ...
Page 14
... CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. The SFRs of the C504 are listed in table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of the C504. Table 3 illustrates the contents of the SFRs in numeric order of their addresses ...
Page 15
... C504 Reset XX10XXX0 B 0X000000 B 3) XX000000 XX000000 B 3) XX000000 B 3) 00101010 XXXX1111 B ...
Page 16
... C504 Reset 00 H XXXXXXX0 00010000 ...
Page 17
... SM2 REN TB8 . IE2 I2ETF I2ETR I1ETF . – ET2 ES ET1 – ECT1 ECCM ECT2 INT1 17 C504 Bit 2 Bit 1 Bit GF0 PDE IDLE IT1 IE0 IT0 – – – ...
Page 18
... TREN5 TREN4 TREN3 TREN2 TREN1 TREN0 AC F0 RS1 RS0 . C504 Bit 2 Bit 1 Bit 0 EAN4 – – – – XMAP PX1 PT0 PX0 PCEM PX2 PADC SWDT CLK2 CLK1 CLK0 . ...
Page 19
... CMSEL CMSEL CMSEL CMSEL CMSEL 23 CC2R CC1F . C504 Bit 2 Bit 1 Bit 0 – – CC1 CC0 CC0 REN FEN REN BCEN BCM1 BCM0 MX2 MX1 MX0 . – – ...
Page 20
... Figure 5 Timer/Counter 0 and 1 Input Clock Logic Semiconductor Group TMOD Gate C /24. External inputs INT0 and INT1 (P3.2, P3.3) can be OSC 20 C504 Input Clock internal external (max OSC 12 32 OSC OSC 12 OSC 24 f ...
Page 21
... OSC f (falling edge) Down counting Up counting 16 bit Timer/ Counter (only up-counting) f /12 OSC capture TH2, f TL2 RC2H, RC2L no overflow interrupt request (TF2 OSC f extra external interrupt (“Timer 2”) Timer 2 stops – C504 max /24 OSC max /24 OSC max /24 OSC – ...
Page 22
... Capture/Compare Unit The Capture / Compare Unit (CCU) of the C504 is built 16-bit 3-channel capture/compare unit (CAPCOM) and a 10-bit 1-channel compare unit (COMP). In compare mode, the CAPCOM unit provides two output signals per channel, which can have inverted signal polarity and non- overlapping pulse transitions ...
Page 23
... Figure 7 Basic Operating Modes of the CAPCOM Unit Compare timer 1 runs only in operating mode 1 with one output signal of selectable signal polarity at the pin COUT3. Semiconductor Group / /256. The compare timer operations with OSC OSC 23 C504 ...
Page 24
... T D outputs the shift clock. 8-bit are transmitted/received (LSB first) 8-bit UART 10 bits are transmitted (through received ( /32 or /64 9-bit UART OSC OSC 11 bits are transmitted ( received (R D) 9-bit UART Like mode 2 except the variable baud rate 24 C504 ...
Page 25
... Formulas for Calculating Baudrates Baud Rate derived from Oscillator Timer 1 (16-bit timer) (8-bit timer with 8-bit autoreload) Timer 2 Semiconductor Group Interface Mode 0 2 1,3 (2 1,3 (2 SMOD f 1,3 OSC 25 Baudrate f /12 OSC f (2 SMOD ) / 64 OSC SMOD timer 1 overflow rate) / (32 12 (256-TH1)) OSC / (32 (65536-(RC2H, RC2L)) C504 ...
Page 26
... A/D Converter The C504 has a high performance 10-bit A/D converter (figure 9) with 8 inputs included which uses successive approximation technique for the conversion of analog input voltages. Figure 9 A/D Converter Block Diagram Semiconductor Group 26 C504 ...
Page 27
... The A/D converter uses two clock signals for operation : the conversion clock f the input clock Both clock signals are derived from the C504 system clock applied at the XTAL pins. The duration of an A/D conversion is a multiple of the period of the f clock signal. The table in figure 10 shows the prescaler ratios and the resulting A/D conversion times which must be selected for typical system clock rates ...
Page 28
... Interrupt System The C504 provides 12 interrupt sources with two priority levels. Figure 11 and 12 give a general overview of the interrupt sources and illustrate the interrupt request and control flags. Figure 11 Interrupt Request Sources (Part 1) Semiconductor Group 28 C504 ...
Page 29
... Figure 12 Interrupt Request Sources (Part 2) Semiconductor Group 29 C504 ...
Page 30
... Compare timer 2 interrupt Capture / compare match interrupt Compare timer 1 interrupt Power-down interrupt Low Priority A/D Converter External Interrupt 2 CCU Emergency Interrupt Compare Timer 2 Interrupt Capture / Compare Match Interrupt Compare Timer 1 Interrupt 30 C504 Vector Address 0003 H 000B H 0013 H 001B H 0023 H 002B H 0043 H 004B H 0053 H 005B H ...
Page 31
... Oscillator Watchdog Watchdog Timer The watchdog timer in the C504 is a 15-bit timer, which is incremented by a count rate of either /32. From the 15-bit watchdog timer count value only the upper 7 bits can be CYCLE programmed ...
Page 32
... Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency lower than the frequency of an auxiliary RC oscillator, the internal clock is supplied by this RC oscillator and the C504 is put into reset state; if the failure condition again disappears, the part executes a final reset phase of typ order to allow the oscillator to stabilize ...
Page 33
... Two power down modes are available, the idle mode and power down mode. – In the idle mode the oscillator of the C504 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D converter, and all timers with the exception of the watchdog timer are further provided with the clock ...
Page 34
... During overload conditions ( V Voltage on pins with respect to ground ( CC absolute maximum ratings. Semiconductor Group T ) .............................................................. 0 ˚ ˚ ............................................– ..............................................– 0 must not exceed the values defined by the SS 34 C504 > or < ) the ...
Page 35
... 0.9 OH1 CC V 2.4 OH2 0 – – – – – for the SAB-C504 for the SAF-C504 for the SAH-C504 for the SAK-C504 Unit Test Condition max. V 0.2 – V – CC 0.1 V 0.2 – V – CC 0.3 0 – 0.5 V – 0.5 V – ...
Page 36
... 5 all other pins are disconnected. AGND SS V – 0.5 V; XTAL2 = N.C would be slightly higher if a crystal CC – 0.5 V; XTAL2 = N.C – 0.5 V). The supply voltage SS C504 ALE and CC SS ...
Page 37
... min = 500 OSC CLCL 37 for the SAB-C504 for the SAF-C504 for the SAH-C504 for the SAK-C504 Unit Test Condition Prescaler 32 Prescaler 16 Prescaler 8 2) Prescaler 4 ns Prescaler 32 Prescaler ...
Page 38
... S , the time for determining the digital result and the time for the S depend on programming and can be taken from the table on ADC = 4 guaranteed by design characterization for all AGND CC 38 C504 . S ...
Page 39
... Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN *) Interfacing the C504 to devices with float times permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group = ...
Page 40
... AC Characteristics for C504-L / C504-2R (cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE Address valid ...
Page 41
... Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN *) Interfacing the C504 to devices with float times permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group = ...
Page 42
... AC Characteristics for C504-L24 / C504-2R24 (cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE Address valid high to ALE high ...
Page 43
... Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN *) Interfacing the C504 to devices with float times permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group = ...
Page 44
... AC Characteristics for C504-L40 / C504-2R40 (cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE Address valid high to ALE high ...
Page 45
... Figure 15 Program Memory Read Cycle Figure 16 Data Memory Read Cycle Semiconductor Group 45 C504 ...
Page 46
... Figure 17 Data Memory Write Cycle Figure 18 External Clock Cycle Semiconductor Group 46 C504 ...
Page 47
... ROM Verification Characteristics for C504-2R ROM Verification Mode 1 Parameter Address to valid data ENABLE to valid data Data float after ENABLE Oscillator frequency Figure 19 ROM Verification Mode 1 Semiconductor Group Symbol Limit Values min. t – AVQV t – ELQV t 0 EHQZ CLCL 47 C504 Unit max ...
Page 48
... ROM Verification Mode 2 Semiconductor Group Symbol Limit Values min. typ t – AWD CLCL t t – 12 ACY CLCL t – – DVA – DSA CLCL t – CLCL – CLCL 48 C504 Unit max. – ns – CLCL – ns – MHz ...
Page 49
... Figure 22 AC Testing : Float Waveforms Figure 23 Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group V – 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’ for a logic ’1’ and IHmin ILmax 49 C504 for a logic ’0’ level occurs ...