CY2308SI-1T CYPRESS [Cypress Semiconductor], CY2308SI-1T Datasheet

CY2308SI-1T

Manufacturer Part Number

CY2308SI-1T

Description

3.3 V Zero Delay Buffer

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY2308SI-1T.pdf (18 pages)

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3.3 V Zero Delay Buffer

Features

■

Functional Description

The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute

high speed clocks in PC, workstation, datacom, telecom, and

other high performance applications.

The part has an on-chip PLL that locks to an input clock

presented on the REF pin. The PLL feedback is driven from

external FBK pin, so user has flexibility to choose any one of the

outputs as feedback input and connect it to FBK pin. The

input-to-output skew is less than 250 ps and output-to-output

skew is less than 200 ps.

Cypress Semiconductor Corporation

Document Number: 38-07146 Rev. *M

Logic Block Diagram

Zero input-output propagation delay, adjustable by capacitive

load on FBK input

Multiple configurations, see

on page 4

Multiple low skew outputs

Two banks of four outputs, three-stateable by two select inputs

10 MHz to 133 MHz operating range

75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)

Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP

3.3 V operation

Industrial temperature available

for more details

REF

Available CY2308 Configurations

Extra Divider (–5H)

Extra Divider (–3, –4)

•

Extra Divider (–2, –3)

Select Input

198 Champion Court

Decoding

PLL

MUX

The CY2308 has two banks of four outputs each that is controlled

by the select inputs as shown in the table

on page 3.

three-stated. The input clock is directly applied to the output for

chip and system testing purposes by the select inputs.

The CY2308 PLL enters a power down state when there are no

rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off resulting in less than 25 A

of current draw. The PLL shuts down in two additional cases as

shown in the table

Multiple CY2308 devices accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is less than 700 ps.

The CY2308 is available in five different configurations as shown

in the table

■

The CY2308-1 is the base part where the output frequencies

equal the reference if there is no counter in the feedback path.

The CY2308-1H is the high drive version of the -1 and rise and

fall times on this device are much faster.

The CY2308-2 enables the user to obtain 2x and 1x frequencies

on each output bank. The exact configuration and output

frequencies depend on the user’s selection of output that drives

the feedback pin.

The CY2308-3 enables the user to obtain 4x and 2x frequencies

on the outputs.

The CY2308-4 enables the user to obtain 2x clocks on all

outputs. Thus, the part is extremely versatile and is used in a

variety of applications.

The CY2308-5H is a high drive version with REF/2 on both

banks.

•

Available CY2308 Configurations on page

San Jose

If all output clocks are not required, Bank B is

3.3 V Zero Delay Buffer

Select Input Decoding on page

CA 95134-1709

FBK

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Revised October 11, 2011

Select Input Decoding

•

408-943-2600

CY2308

[+] Feedback

Related parts for CY2308SI-1T

CY2308SI-1T Summary of contents

Page 1

V Zero Delay Buffer Features Zero input-output propagation delay, adjustable by capacitive ■ load on FBK input Multiple configurations, see Available CY2308 Configurations ■ on page 4 for more details Multiple low skew outputs ■ Two banks of four ...

Page 2

Contents Pinouts .............................................................................. 3 Pin Definitions - 16-pin SOIC ........................................... 3 Select Input Decoding ...................................................... 3 Available CY2308 Configurations ................................... 4 Zero Delay and Skew Control .......................................... 4 Maximum Ratings ............................................................. 5 Operating Conditions for Commercial Temperature Devices .................................. 5 ...

Page 3

Pinouts Figure 1. Pin Diagram - 16-pin SOIC (Top View) Pin Definitions - 16-pin SOIC Pin Signal [1] 1 Input reference frequency REF [2] 2 Clock output, Bank A CLKA1 [2] 3 Clock output, Bank A CLKA2 4 V Power ...

Page 4

Available CY2308 Configurations Device Feedback From CY2308-1 Bank A or Bank B CY2308-1H Bank A or Bank B CY2308-2 Bank A CY2308-2 Bank B CY2308-3 Bank A CY2308-3 Bank B CY2308-4 Bank A or Bank B CY2308-5H Bank A or ...

Page 5

Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Supply voltage to ground potential ..............–0 +7 input voltage (except REF) ........... –0 Operating Conditions ...

Page 6

Switching Characteristics for Commercial Temperature Devices [9] Parameter Name F Input frequency in t Output frequency 1 t Output frequency 1 t Output frequency 1 [9] t t Duty cycle = (-1, -2, -3, -4, -1H, ...

Page 7

Operating Conditions for Industrial Temperature Devices Parameter V Supply voltage DD T Operating temperature (ambient temperature Load capacitance, below 100 MHz L Load capacitance, from 100 MHz to 133 MHz [10] C Input capacitance IN t Power up ...

Page 8

Switching Characteristics for Industrial Temperature Devices [13] Parameter Name F Input frequency in t Output frequency 1 t Output frequency 1 t Output frequency 1 [13, 14] t t Duty cycle = (-1, -2, -3, -4, -1H, ...

Page 9

Switching Waveforms 1.4V OUTPUT OUTPUT OUTPUT INPUT FBK FBK, Device 1 FBK, Device 2 Document Number: 38-07146 Rev. *M Figure 3. Duty Cycle Timing 1.4V 1.4V Figure 4. All Outputs Rise/Fall Time 2.0V 2.0V 0.8V 0.8V ...

Page 10

Typical Duty Cycle and I Trends DD [15, 16] For CY2308- Duty Cycle (for 30 pF Loads over Frequency - 3.3V, 25C ...

Page 11

Typical Duty Cycle and I Trends DD [17, 18] For CY2308-1H, 5H Duty Cycle (for 30 pF Loads over Frequency - 3.3V, 25C 3.1 3.2 ...

Page 12

Test Circuits Test Circuit 0.1 F Outputs V DD 0.1 F GND GND Test Circuit for all parameters except t Document Number: 38-07146 Rev. *M Test Circuit 0.1 F CLK OUT C LOAD V ...

Page 13

... Ordering Information Ordering Code [19] CY2308SI-1T 16-pin 150 mil SOIC - Tape and Reel [19] CY2308ZI-1H 16-pin 4.4 mm TSSOP [19] CY2308ZI-1HT 16-pin 4.4 mm TSSOP - Tape and Reel [19] CY2308SI-2 16-pin 150 mil SOIC [19] CY2308SI-2T 16-pin 150 mil SOIC - Tape and Reel Pb-free CY2308SXC-1 16-pin 150 mil SOIC CY2308SXC-1T ...

Page 14

Ordering Code Definitions CY 2308 Document Number: 38-07146 Rev blank T = Tape and Reel; blank = Tube Dash or Variant Code Temperature Range ...

Page 15

Package Diagrams Figure 8. 16-pin SOIC (150 Mil) S16.15 Package Outline, 51-85068 Figure 9. 16-pin TSSOP 4.40 mm Body Z16.173 Package Outline, 51-85091 Document Number: 38-07146 Rev. *M CY2308 51-85068 *D 51-85091 *D Page [+] Feedback ...

Page 16

Acronyms Table 1. Acronyms Used in this Document Acronym Description FBK feedback PLL phase locked loop MUX multiplexer Document Conventions Units of Measure Table 2. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fC femtocoulomb fF ...

Page 17

... Updated template. Added Note 19 “Not recommended for new designs.” Changed IDD (PD mode) from 12.0 to 25.0 A for Commercial and Industrial Temperature Devices Deleted Duty Cycle parameters for F Removed CY2308SI-4, CY2308SI-4T and CY2308SC-5HT. 01/08/09 Corrected TSSOP package size (from 150 mil to 4.4 mm) in Ordering Information table ...

Page 18

Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive cypress.com/go/automotive Clocks & ...

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