CY2304-2 CYPRESS [Cypress Semiconductor], CY2304-2 Datasheet

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CY2304-2

Manufacturer Part Number
CY2304-2
Description
3.3V Zero Delay Buffer
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Cypress Semiconductor Corporation
Document #: 38-07247 Rev. *C
Features
Functional Description
The CY2304 is a 3.3V zero delay buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom, and
other high-performance applications.
• Zero input-output propagation delay, adjustable by
• Multiple configurations – see “Available Configura-
• Multiple low-skew outputs
• 10-MHz to 133-MHz operating range
• Low jitter, less than 200 ps cycle-cycle
• Space-saving 8-pin 150-mil SOIC package
• 3.3V operation
• Industrial temperature available
REF
capacitive load on FBK input
tions” table
— Output-output skew less than 200 ps
— Device-device skew less than 500 ps
Logic Block Diagram
Available Configurations
CY2304-1
CY2304-2
CY2304-2
Device
Bank A or B
FBK from
Bank A
Bank B
PLL
Bank A Frequency Bank B Frequency
3901 North First Street
/2
2 × Reference
Reference
Reference
Extra Divider (-2)
The part has an on-chip phase-locked loop (PLL) that locks to
an input clock presented on the REF pin. The PLL feedback is
required to be driven into the FBK pin, and can be obtained
from one of the outputs. The input-to-output skew is
guaranteed to be less than 250 ps, and output-to-output skew
is guaranteed to be less than 200 ps.
The CY2304 has two banks of two outputs each.
The CY2304 PLL enters a power-down state when there are
no rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
25 A of current draw.
Multiple CY2304 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 500 ps.
The CY2304 is available in two different configurations, as
shown in the “Available Configurations” table. The CY2304–1
is the base part, where the output frequencies equal the
reference if there is no counter in the feedback path.
The CY2304–2 allows the user to obtain Ref and 1/2x or 2x
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the
feedback pin.
Reference/2
Reference
Reference
CLKA1
CLKB2
CLKA2
CLKB1
FBK
San Jose
3.3V Zero Delay Buffer
CLKA1
CLKA2
GND
REF
Pin Configuration
CA 95134
Revised December 7, 2002
1
2
3
4
8-pin SOIC
Top View
8
7
6
5
408-943-2600
FBK
V
CLKB1
CLKB2
DD
CY2304

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CY2304-2 Summary of contents

Page 1

... Device FBK from CY2304-1 Bank CY2304-2 Bank A CY2304-2 Bank B Cypress Semiconductor Corporation Document #: 38-07247 Rev. *C The part has an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs ...

Page 2

... Zero Delay and Skew Control REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins To close the feedback loop of the CY2304, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load plus any additional load that it drives ...

Page 3

... Input HIGH Current IH V Output LOW Voltage OL V Output HIGH Voltage OH I (PD mode) Power-down Supply Current REF = 0 MHz DD I Supply Current DD Switching Characteristics for CY2304SC-X Commercial Temperature Devices Parameter Name t Output Frequency 1 t Output Frequency 1 [4] Duty Cycle = (–1,–2) ...

Page 4

... Parameter V Supply Voltage DD T Operating Temperature (Ambient Temperature Load Capacitance (below 100 MHz) L Load Capacitance (from 100 MHz to 133 MHz) C Input Capacitance IN Switching Characteristics for CY2304SI-X Industrial Temperature Devices Parameter Name t Output Frequency 1 t Output Frequency 1 [4] Duty Cycle = (– ...

Page 5

... Switching Characteristics for CY2304SI-X Industrial Temperature Devices Parameter Name t Output-to-Output Skew on 5 [4] same Bank (–1,–2) Output Bank A to Output Bank B Skew (–1) Output Bank A to Output Bank B Skew (–2) t Skew, REF Rising Edge to 6 [4] FBK Rising Edge t Device-to-Device Skew ...

Page 6

... INPUT V DD FBK t 6 Device-Device Skew FBK, Device 1 FBK, Device Test Circuits 0.1 0.1 Document #: 38-07247 Rev. *C 3.3V 2.0V 0. Test Circuit # OUTPUTS GND GND Test circuit for all parameters except t CY2304 CLK OUT C LOAD 8 Page ...

Page 7

... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Type S8 8-pin 150-mil SOIC S8 8-pin 150-mil SOIC S8 8-pin 150-mil SOIC S8 8-pin 150-mil SOIC 8-lead (150-Mil) SOIC S8 CY2304 Operating Range Commercial Industrial Commercial Industrial 51-85066-A Page ...

Page 8

... Document Title: CY2304 3.3V Zero Delay Buffer Document Number: 38-07247 REV. ECN N0. Issue Date ** 110512 12/11/01 *A 112294 03/04/02 *B 113934 05/01/02 *C 121851 12/14/02 Document #: 38-07247 Rev. *C Orig. of Change Description of Change SZV Change from Spec number: 38-01010 to 38-07247 CKN On Pin Configuration Diagram (p.1), swapped CLKA2 and CLKA1 CKN Added Operating Conditions for CY2304SI-X Industrial Temperature Devices, p ...

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