zr36067 ETC-unknow, zr36067 Datasheet - Page 34

• Manufacturer Part Number: zr36067
• Description: Av Pci Controller
• Manufacturer: ETC-unknow

AV PCI CONTROLLER
Address Offset: 0x104
13.22 Vertical Sync Parameters
This register contains the VSYNC parameters to be generated
by the ZR36067 as a sync master.
Address Offset: 0x108
13.23 Horizontal Sync Parameters
This register contains the HSYNC parameters to be generated
by the ZR36067 as a sync master.
Address Offset: 0x10C
13.24 Field Horizontal Active Portion
This register contains the horizontal parameters of the active
portion of the processed field.
Address Offset: 0x110
31 : 16
31 : 16
31: 24
23: 16
15 : 0
15 : 0
15 : 0
4 : 1
Bit
Bit
Bit
Bit
0
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
R
Mod
Mod
Mod
Mod
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Reserved, Returns zero.
Active - This command bit is asserted by the
host in order to initiate a JPEG process.
‘1’ - Active is asserted.
‘0’ - Active is deasserted.
Default value is ‘0’.
Reserved. Returns zero.
VsyncSize - VSYNC signal length. The
VSYNC length is measured in lines.
Default value is 0x06.
FrmTot - Frame total size. The total number
of lines per frame. This parameter must be an
odd number.
Default Value is 0x020D (525, for NTSC)
HsyncStart - HSYNC signal Start point.
The point in the line (measured in number of
VCLKs) at which HSYNC should be asserted.
Default value is 0x0280 (640, for square pixel
NTSC).
LineTot - Line total size. The total number
VCLKs in a line.
Default Value is 0x030C (780, for square
pixel NTSC)
NAX - The first pixel in a line to be processed.
Counted from the active edge of HSYNC.
Default value is 0x0000.
PAX - The number of pixels to be processed
in a line.
Default Value is 0x0280 (640, for square pixel
NTSC)
Description
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13.25 Field Vertical Active Portion
This register contains the vertical parameters of the active
portion of the processed field.
Address Offset: 0x114
13.26 Field Process Parameters
This register contains the general parameters of the field
process.
Address Offset: 0x118
13.27 JPEG Code Base Address
This register specifies the base address of the code buffer table.
Address Offset: 0x11C
13.28 JPEG Code FIFO Threshold
This register specifies Code FIFO threshold in JPEG mode.
Address Offset: 0x120
31 : 16
15 : 0
31 : 1
31 : 0
31 : 8
7 : 0
Bit
Bit
Bit
Bit
0
Type
Type
Type
Type
RW
RW
RW
RW
RW
R
R
Mod
Mod
Mod
Mod
jpg
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jpg
jpg
jpg
NAY - The first line in a field to be processed.
Counted from the active edge of VSYNC.
Default value is 0x000A.
PAY - The number of lines to be processed in
a field.
Default Value is 0x00F0 (240, for NTSC)
Reserved. Returns zero.
Odd_Even - First field type. The type of the
first field to be processed. Odd type is defined
as the field in which the active edge of
VSYNC is asserted during the active portion
of the horizontal line. Even type is defined as
the field in which the active edge of VSYNC is
asserted during the active portion of HSYNC.
‘1’ - The first field is Odd.
‘0’ - The first field is Even.
Default value is ‘1‘.
I_STAT_COM_PTR - The memory address
of the code buffer table.
Default value 0xFFFFFFFC.
Reserved, Returns zero.
JPEGCodTrshld - JPEG code FIFO Thresh-
old. In Compression, if the fullness level of
the Code FIFO (in doublewords) goes above
this threshold the PCI bus is requested.
In Decompression, if the fullness level of the
Code FIFO (in doublewords) goes under this
threshold the PCI bus is requested.
Default value is 0x50h
Description
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