DS90UR124IVS NSC [National Semiconductor], DS90UR124IVS Datasheet - Page 5

• Manufacturer Part Number: DS90UR124IVS
• Description: 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
• Manufacturer: NSC [National Semiconductor]

t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RxIN_TOL-L
RxIN_TOL-R Receiver INput TOLerance
ROS
ROH
ROS
ROH
ROS
ROH
ROS
ROH
ROS
ROH
ROS
ROH
HZR
LZR
ZHR
ZLR
DD
DSR
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 5: t
Note 6: RxIN_TOL is a measure of how much phase noise (jitter) the Deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 7: Guaranteed by Design (GBD) using statistical analysis.
Note 8: t
Note 9: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 10: Figures 1, 2, 9, 10, 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 11: Figures 6, 11, 12 show a rising edge data strobe (TCLK IN/RCLK OUT).
Note 12: TxOUT_E_O is affected by pre-emphasis value.
Symbol
DSR
JIT
(
@
is the time required by the Deserializer to obtain lock when exiting powerdown mode.
BER of 10e-9) specifies the allowable jitter on TCLK. t
R
RCLK (Group 1)
R
RCLK (Group 1)
R
RCLK (Group 2)
R
RCLK (Group 2)
R
to RCLK (Group 3)
R
to RCLK (Group 3)
R
RCLK (Group 1)
R
RCLK (Group 1)
R
RCLK (Group 2)
R
RCLK (Group 2)
R
to RCLK (Group 3)
R
to RCLK (Group 3)
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer Delay
Deserializer PLL Lock Time
from Powerdown
Receiver INput TOLerance
Left
Right
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
(0:7) Setup Data to
(0:7) Hold Data to
(8:15) Setup Data to
(8:15) Hold Data to
(16:23) Setup Data
(16:23) Setup Data
(0:7) Setup Data to
(0:7) Hold Data to
(8:15) Setup Data to
(8:15) Hold Data to
(16:23) Setup Data
(16:23) Setup Data
Parameter
DD
= 3.3V and T
PTOSEL = L,
(Figure 12)
PTOSEL = H,
(Figure 11)
PTOSEL = H,
(Figure 13)
PTOSEL = H,
(Figure 10)
(Notes 5, 7)
(Notes 6, 9),
(Figure 16)
(Notes 6, 9),
(Figure 16)
A
= +25˚C.
Conditions
JIT
not included in TxOUT_E_O parameter.
R
R
LOCK
R
R
R
LOCK
R
R
RCLK, LOCK
RCLK
5 MHz
43 MHz
5 MHz–43 MHz
5 MHz–43 MHz
5
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Pin/Freq.
(Continued)
[0:7]
[0:7]
[8:15],
[16:23]
[8:15],
[16:23]
[0:23],
(0.35)*
(0.35)*
(0.35)*
(0.35)*
(0.35)*
(0.35)*
(0.35)*
(0.35)*
(0.35)*
(0.35)*
(0.35)*
(0.35)*
0.25
0.25
t
t
t
t
t
t
t
t
t
t
t
t
Min
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
(0.5*t
(0.5*t
(0.5*t
(0.5*t
(0.5*t
(0.5*t
(0.5*t
(0.5*t
[5+(5/56)]T+3.7
(0.5*t
(0.5*t
(0.5*t
(0.5*t
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
Typ
3
3
3
3
)–3 UI
)–3 UI
)–3 UI
)–3 UI
)–3 UI
)–3 UI
)–2 UI
)+2 UI
)−1 UI
)+1 UI
)+1 UI
)–1 UI
[5+(5/56)]T
128k*T
128k*T
Max
10
10
10
10
+8
www.national.com
Units
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UI
UI