DS1073 DALLAS [Dallas Semiconductor], DS1073 Datasheet
DS1073
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DS1073 Summary of contents
Page 1
... The choice of reference source (internal or external) is user-selectable at the time of programming (or on the fly if the SEL mode is chosen). The DS1073 features a dual-purpose I/O pin. If the device is powered up in Program mode this pin can be used to input serial data to the on chip registers. After a Write command this data is stored in non-volatile memory ...
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... The DS1073 is available in 8-pin DIP or SOIC packages, allowing the generation of a clock signal easily, economically and using minimal board area. BLOCK DIAGRAM Figure 1 PART INTOSC NO. FREQUENCY SUFFIX -100 100.000 MHz -80 80.000 MHz -66 66.667 MHz -60 60.000 MHz ...
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... The crystal must be used in fundamental mode crystal is not used this pin should be left open. Output Enable Function (OE pin): The DS1073 also features a “synchronous” output enable. When high logic level the oscillator free runs. When this pin is taken low OUT is held low, immediately if OUT is already low its next high-to-low transition if OUT is high ...
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USER-PROGRAMMABLE REGISTERS The following registers can be programmed by the user to determine operating frequency and mode of operation. Details of how these registers are programmed can be found in a later section, in this section the function of the ...
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Table 2 DIV1 E/ I MSEL BIT BIT* BIT *Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the DIV WORD ...
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... Since the output enable, internal master oscillator and/or external master oscillator are likely all asynchronous there is the possibility of timing difficulties in the application. difficulties the DS1073 features an “enabling sequencer” to produce predictable results when the device is enabled and disabled. In particular the output gating is configured so that truncated output pulses can never be produced ...
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Figure 6 SELECT TIMING If the PDN bit is set to 0, the externalor crystal reference. The “Enabling Sequencer” is again employed to ensure this transition occurs in a glitch-free fashion. Two asynchronous clock signals are involved, INTCLK is the ...
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FROM EXTERNAL TO INTERNAL CLOCK This is accomplished by a low to high transition on the triggered, to allow for the possibility of a clock signal not being present at OSCIN. Note therefore, that if a constant high-level signal is ...
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POWER-UP When is taken to a high level the following power-up sequence occurs: PDN 1. Enable internal oscillator and/or OSCIN buffer. 2. Set M and N to maximum values. 3. Wait approximately 256 cycles of MCLK for it to stabilize. ...
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... The hardware configuration is shown in the diagram. A bus master is used to read and write data to the DS1073’s internal registers. The bus master may have either an open drain or TTL-type architecture. Figure 11 Programming mode is entered by simply powering up the DS1073 with a pullup of approximately 5kW. This will pull the I/O pin above V DS1073 to internally release the I/O pin (after t supply rail and await the Master Tx Reset pulse (see diagram). ä ...
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... All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the DS1073. The presence pulse lets the bus master know that the DS1073 is present and is ready to operate. Figure 13 FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the four function commands ...
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... DS1073. During write time slots, the delay circuit determines when the DS1073 will sample the data line. For a read data time slot transmitted, the delay circuit determines how long the DS1073 will hold the data line low overriding the 1 generated by the master. If the data bit the DS1073 will leave the read data time slot unchanged ...
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... READ DATA TIME SLOT Figure 16 RETURN TO NORMAL OPERATION When programming is complete the DS1073 should be powered down. If the pullup resistor on the I/O pin is removed, normal device operation will be restored next time power is applied. DEFAULT REGISTER VALUES Unless ordered from the factory with specific register program values, the DS1073 is shipped with the ...
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... Low-level Input Voltage High-level Input Current ( , OE) PDN / SELX (OSCIN) Low-level Input Current( , OE) PDN / SELX (OSCIN) Supply Current (Active) DS1073-100 DS1073-80 DS1073-66 DS1073-60 Standby Current (power-down) -1.0V to +7.0V 0°C to 70°C -55°C to +125°C See J - STD-020A (T = 0°C to +70° SYMBOL CONDITION ...
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AC ELECTRICAL CHARACTERISTICS (T PARAMETER Output Frequency Accuracy Combined Frequency Variation Long Term Stability Maximum Input Frequency Minimum Output Frequency Power-Up Time Enable OUT from PDN ↑ Enable OUT0 from PDN ↑ I/O Hi-Z from PDN ↓ OUT0 Hi-Z from ...
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AC ELECTRICAL CHARACTERISTICS – CALCULATED PARAMETERS The following characteristics are derived from various device-operating parameters (frequency, mode, etc.). They are not specifically tested or guaranteed and may differ from the min and max limits shown by a small amount due ...
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... OUT0) High-level Input Voltage Low-level Input Voltage High-level Input Current ( , OE) PDN / SELX (OSCIN) Low-level Input Current( , OE) PDN / SELX (OSCIN) Supply Current (Active) DS1073-100 DS1073-80 DS1073-66 DS1073-60 Standby Current (power-down -40°C to +85° SYMBOL CONDITION mA MIN ...
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AC ELECTRICAL CHARACTERISTICS PARAMETER Output Frequency Accuracy Combined Frequency Variation Long Term Stability Maximum Input Frequency Minimum Output Frequency Power-Up Time Enable OUT from PDN ↑ Enable OUT0 from PDN ↑ I/O Hi-Z from PDN ↓ OUT0 Hi-Z from PDN ...