f75387 Feature Integration Technology Inc., f75387 Datasheet - Page 24

• Manufacturer Part Number: f75387
• Description: ?1o C Accuracy H/w Monitor Ic With Automatic Fan Speed Control
• Manufacturer: Feature Integration Technology Inc.

Note: Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts won’t be
Power-on default [7:0] =0000_0000 b
8.7.
Bit
2A h
7
6
5
4
3
2
1
0
1Dh
1Eh
2Bh
2Ch
2Dh
2Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Fh
generated except the case when voltages go below the low limits.
EN_FAN2_SMI
EN_FAN1_SMI
EN_VT2_SMI
EN_VT1_SMI
EN_V3_SMI
EN_V2_SMI
EN_V1_SMI
EN_VCC_SMI
IRQ/SMI# ENABLE Register 1  Index 30h
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
-
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3Ch
FFh
FFh
FFh
FFh
5Fh
5Fh
00h
00h
00h
00h
64h
64h
37h
00h
-
Local Temperature reading (LSB). The unit is 1/256
The V1 – VCC value. The MSB and LSB are in the same index. To read the whole
register, read this register twice continuously.
The V3 – V2 value. The MSB and LSB are in the same index. To read the whole
register, read this register twice continuously.
VCC High Limit. The unit is 8mV. The last two LSBs are fixed to 2’b11.
VCC Low Limit. The unit is 8mV. The last two LSBs are fixed to 2’b00.
V1 High Limit. The unit is 8mV. The last two LSBs are fixed to 2’b11.
V1 Low Limit. The unit is 8mV. The last two LSBs are fixed to 2’b00.
V2 High Limit. The unit is 8mV. The last two LSBs are fixed to 2’b11.
V2 Low Limit. The unit is 8mV. The last two LSBs are fixed to 2’b00.
V3 High Limit. The unit is 8mV. The last two LSBs are fixed to 2’b11.
V3 Low Limit. The unit is 8mV. The last two LSBs are fixed to 2’b00.
Temperature sensor 1 High Limit. The unit is 1
Temperature sensor 1 Hysteresis Limit. The unit is 1
Temperature sensor 2 High Limit. The unit is 1
Temperature sensor 2 Hysteresis Limit. The unit is 1
Local Temperature sensor High Limit. The unit is 1
Local Temperature sensor Hysteresis Limit. The unit is 1
External register value.
Reserved
A one enables the corresponding interrupt status bit for SMI# interrupt
A one enables the corresponding interrupt status bit for SMI# interrupt.
A one enables the corresponding interrupt status bit for SMI# interrupt.
A one enables the corresponding interrupt status bit for SMI# interrupt.
A one enables the corresponding interrupt status bit for SMI# interrupt.
A one enables the corresponding interrupt status bit for SMI# interrupt.
A one enables the corresponding interrupt status bit for SMI# interrupt.
A one enables the corresponding interrupt status bit for SMI# interrupt.
22
Description
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July, 2007
F75387
0.27P