ax88796 ASIX Electronics Corporation, ax88796 Datasheet - Page 69

• Manufacturer Part Number: ax88796
• Description: Non-pci 8/16-bit 10/100m Fast Ethernet Controller With Embedded Phy
• Manufacturer: ASIX Electronics Corporation

Errata of AX88796
1. MII Station Management functions have some difference from previous target specification.
Description: The target specification is using station management can access both internal
PHY registers and external PHY registers when the PHY address is matched as describe in
section 5.5. Anyway, this version can only access the current selected PHY’s registers. How do
you know which is the selected media or PHY? Please refer to section 4.1.16 GPO and Control
(GPOC) register.
Solution: The defect will not affect single media application that is using embedded PHY.
When using MII interface connects to external media (for example HomePNA) to come out
with combo solution. Care must be taken, be sure which media is the current selected when you
access PHY registers.
2. AX88796 can’t support 68K CPU with byte mode
Solution: Please using word mode for high performance. MC68008 has only 8-bit bus, so
AX88796 can’t support this CPU.
3. When AX88796 transmit a packet and the packet is collided for 16 times. The packet will be
reported as as PTX bit asserted rather than TXE asserted.
Solution: Packet collided 16 times and aborted is normal way, even that is rare happen in live
network, in very heavy traffic. While the upper protocol layer will handle the situation and
cover the packet loss.
4. Some chips may need long power down for successful PHY auto negotiation
Description: The PHY inside of AX88796 has a special request due to the semiconductor’s
process. Namely, it needs a very long power down for successful Auto Negotiation for some
chips. We made a test in lab and found it would be no problem if the PHY's initial time kept for
2 sec for all chips. If the power down is less then this number, some of the PHY's Auto
Negotiation will not be complete and there will be potential to cause the link fail. If the auto
negotiation time is not long enough, uncertain numbers of chip may not work properly.
Countermeasure:
Following actions will fix the problem of long auto negotiation.
1. Set the PHY register MR0 with 0x800h (1000,0000,0000) -- bit 11 of MR0 to '1'
2. Wait for 2.5 sec
3. Set the PHY register MR0 with 0x1200h(0001,0010,0000,0000) -- bit 12,9 of MR0
AX88796 L
(Power down Mode).
to '1' (auto negotiation enable and restart auto negotiation)
3-in-1 Local Bus Fast Ethernet Controller
69
ASIX ELECTRONICS CORPORATION