ic41c1625 Integrated Silicon Solution, Inc., ic41c1625 Datasheet - Page 5

• Manufacturer Part Number: ic41c1625
• Description: 256k 4-mbit Dynamic With Fast Page Mode
• Manufacturer: Integrated Silicon Solution, Inc.

Integrated Circuit Solution Inc.
DR021-0A 08/11/2001
FUNCTIONAL DESCRIPTION
The IC41C16257 and the IC41LV16257 are CMOS DRAMs
optimized for high-speed bandwidth, low-power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are entered
nine bits (A0-A8) at a time. The row address is latched by the
Row Address Strobe (RAS). The column address is latched
by the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used to latch the latter nine bits.
The IC41C16257 and the IC41LV16257 have two CAS
controls, LCAS and UCAS. The LCAS and UCAS inputs
internally generate a CAS signal functioning in an identical
manner to the single CAS input on the other 256K x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE and
WE and RAS). LCAS controls
controls I/O8 - I/O15.
The IC41C16257/IC41LV16257 CAS function is determined
by the first CAS (LCAS or UCAS) transitioning LOW and the
last transitioning back HIGH. The two CAS controls give the
IC41C16257 both BYTE READ and BYTE WRITE cycle
capabilities.
Memory Cycle
A memory cycle is initiated by bringing RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum t
not be initiated until the minimum precharge time t
elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The column
address must be held for a minimum time specified by t
Data Out becomes valid only when t
all satisfied. As a result, the access time is dependent on the
timing relationships between these parameters.
IC41C16257/IC41C16257S
IC41LV16257/IC41LV16257S
RAS
time has expired. A new cycle must
RAC
I/O0 - I/O7 and UCAS
, t
AA
, t
CAC
and t
RP
, t
CP
OE
has
are
AR
.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs last.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory:
1. By clocking each of the 512 row addresses (A0 through
2. Using a CAS-before-RAS refresh cycle. CAS-before-
CAS-before-RAS is a refresh-only mode and no data access
or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 64 ms. i.e.,
125 µs per row when using distributed CBR refreshes. The
feature also allows the user the choice of a fully static, low
power data retention mode. The optional Self Refresh feature
is initiated by performing a CBR Refresh cycle and holding
RAS LOW for the specified t
The Self Refresh mode is terminated by driving RAS HIGH for
a minimum time of t
of any internal refresh cycles that may be in process at the
time of the RAS LOW-to-HIGH transition. If the DRAM
controller uses a distributed refresh sequence, a burst refresh
is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or burst
refresh sequence, all 512 rows must be refreshed within the
average internal refresh rate, prior to the resumption of normal
operation.
Power-On
After application of the V
200 µs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a RAS signal).
During power-on, it is recommended that RAS track with V
or be held at a valid V
Note:
1.Self Refresh is for Sversion only.
A8) with RAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the ad-
dressed row.
RAS refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle, an
internal 9-bit counter provides the row addresses and the
external address inputs are ignored.
RPS
IH
. This delay allows for the completion
(1)
to avoid current surges.
CC
RASS
supply, an initial pause of
.
CC
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