msm82c55a-2gs Oki Semiconductor, msm82c55a-2gs Datasheet - Page 20

• Manufacturer Part Number: msm82c55a-2gs
• Description: Cmos Programmable Peripheral Interface
• Manufacturer: Oki Semiconductor

¡ Semiconductor
5. Port C Status Read
6. Reset of MSM82C55A-2
Note: Comparison of MSM82C55A-5 and MSM82C55A-2
10
11
6
8
1
2
3
4
5
7
9
MSM82C55A-5
After a write command is executed to the command register, the internal latch is cleared in
PORTA PORTC. For instance, 00H is output at the beginning of a write command when
the output port is assigned. However, if PORTB is not cleared at this time, PORTB is
unstable. In other words, PORTB only outputs ineffective data (unstable value according
to the device) during the period from after a write command is executed till the first data
is written to PORTB.
MSM82C55A-2
After a write command is executed to the command register, the internal latch is cleared in
All Ports (PORTA, PORTB, PORTC). 00H is output at the beginning of a write command
when the output port is assigned.
When port C is used for the control signal, that is, in either mode 1 or mode 2, each control
signal and bus status signal can be read out by reading the content of port C.
The status read out is as follows:
Be sure to keep the RESET signal at power ON in the high level at least for 50 ms.
Subsequently, it becomes the input mode at a high level pulse above 500 ns.
Group A
Mode 2
Mode 2
Mode 1
Mode 1
Mode 0
Mode 0
Mode 1
Mode 1
Mode 1
Mode 2
Mode 1
Output
Output
Output
Input
Input
Input
Group B
Mode 1
Mode 1
Mode 1
Mode 1
Mode 0
Mode 1
Mode 0
Mode 0
Mode 1
Mode 1
Mode 1
Output
Output
Output
Output
Input
Input
Input
Input
OBF
OBF
OBF
OBF
OBF
OBF
I/O
I/O
I/O
I/O
I/O
D
7
A
A
A
A
A
A
INTE
INTE
INTE
INTE
INTE
INTE
D
I/O
I/O
I/O
I/O
I/O
6
A
1
A
A
1
1
IBF
IBF
IBF
IBF
IBF
IBF
D
I/O
I/O
I/O
I/O
I/O
Status Read on the Data Bus
5
A
A
A
A
A
A
INTE
INTE
INTE
INTE
INTE
INTE
I/O
I/O
I/O
I/O
I/O
D
4
2
A
A
A
2
2
INTR
INTR
INTR
INTR
INTR
INTR
INTR
INTR
INTR
I/O
I/O
D
3
A
A
A
A
A
MSM82C55A-2RS/GS/VJS
A
A
A
A
INTE
INTE
INTE
INTE
INTE
INTE
INTE
INTE
I/O
I/O
I/O
D
2
B
B
B
B
B
B
B
B
OBF
OBF
OBF
OBF
IBF
IBF
IBF
IBF
I/O
I/O
I/O
D
1
B
B
B
B
B
B
B
B
INTR
INTR
INTR
INTR
INTR
INTR
INTR
INTR
20/26
I/O
I/O
I/O
D
0
B
B
B
B
B
B
B
B