DM74ALS240ASJX Fairchild Semiconductor, DM74ALS240ASJX Datasheet

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DM74ALS240ASJX

Manufacturer Part Number
DM74ALS240ASJX
Description
IC INVERTER DUAL 4-INPUT 20SOP
Manufacturer
Fairchild Semiconductor
Series
74ALSr
Datasheet

Specifications of DM74ALS240ASJX

Logic Type
Inverter
Number Of Inputs
4
Number Of Circuits
2
Current - Output High, Low
15mA, 24mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-SOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
©1986 Fairchild Semiconductor Corporation
DM74ALS240A, DM74ALS241A Rev. 1.3
DM74ALS240A, DM74ALS241A
Octal 3-STATE Bus Driver
Features
Ordering Information
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
DM74ALS240AWM
DM74ALS240ASJ
DM74ALS240AN
DM74ALS241AWM
Advanced low power oxide-isolated ion-implanted
Schottky TTL process
Functional and pin compatible with the DM74LS
counterpart
Improved switching performance with less power
dissipation compared with the DM74LS counterpart
Switching response specified into 500 and 50pF
load
Switching response specifications guaranteed over
full temperature and V
PNP input design reduces input loading
Low level drive current: 74ALS
Order Number
DM74ALS240A
CC
Package
Number
M20D
M20B
M20B
N20A
supply range
24mA
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
General Description
These octal 3-STATE bus drivers are designed to
provide the designer with flexibility in implementing a bus
interface with memory, microprocessor, or communi-
cation systems. The output 3-STATE gating control is
organized into two separate groups of four buffers.
The DM74ALS240A control inputs symmetrically enable
the respective outputs when set logic LOW, while the
DM74ALS241A has complementary enable gating.
The 3-STATE circuitry contains a feature that maintains
the buffer outputs in 3-STATE (high impedance state)
during power supply ramp-up or ramp-down. This elimi-
nates bus glitching problems that arise during power-up
and power-down.
Package Description
DM74ALS241A
www.fairchildsemi.com
September
2007
tm

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