sp5730 Mitel, sp5730 Datasheet - Page 5

• Manufacturer Part Number: sp5730
• Description: 1.3ghz Low Phase Noise Frequency Synthesiser
• Manufacturer: Mitel

Absolute Maximum Ratings
Functional Description
The SP5730 contains all the elements necessary, with
the exception of a frequency reference, loop filter and
external high voltage transistor, to control a varicap
tuned local oscillator, so forming a complete PLL
frequency synthesised source. The device allows for
operation with a high comparison frequency and is
fabricated in high speed logic, which enables the
generation of a loop with good phase noise performance.
It can also be operated with comparison frequencies
appropriate for frequency offsets as required in digital
terrestrial (DTT) receivers The block diagram is shown
in Figure 2.
The RF input signal is fed to an internal preamplifier,
which provides gain and reverse isolation from the
divider signals. The output of the preamplifier interfaces
direct with the 15-bit fully programmable divider, which
is of MN+A architecture, where the dual modulus
prescaler is 8/9, the A counter is 3-bits, and the M
counter is 12 bits.
The output of the programmable divider is fed to the
phase comparator where it is compared in both phase
and frequency domain with the comparison frequency.
This frequency is derived either from the on-board
crystal controlled oscillator or from an external reference
source. In both cases the reference frequency is divided
down to the comparison frequency by the reference
divider which is programmable into 1 of 29 ratios as
detailed in Table 1.
The output of the phase detector feeds a charge pump
and loop amplifier section, which when used with an
external high voltage transistor and loop filter, integrates
the current pulses into the varactor line voltage.
All voltages are referred to Vee at 0V
RF input voltage
All I/O port DC offsets
SDA and SCL DC offset
Storage temperature
Junction temperature
QP16 thermal resistance,
chip to ambient
chip to case
Power consumption at
Vcc = 5.5V
ESD protection
Supply voltage, Vcc
Characteristic
-0.3
-0.3
-0.3
Min
-55
2
Vcc+0.3
+150
Max
150
2.5
6V
80
20
83
7
The programmable divider output Fpd divided by two
can be switched to port P0 by programming the device
into test mode. The test modes are described in Table 4.
Programming
The SP5730 is controlled by an I
compatible with both standard and fast mode formats
and with I
sources. The I
port P3/LOGLEV. 5V logic levels are selected by
connecting P3/LOGLEV to Vcc or leaving open circuit
and 3.3V by connecting to ground. If this port is used as
an input the P3 data should be programmed to high
impedance. If used as an output 5V logic only levels can
be used and in this case the logic state imposed by the
port on the input is ignored.
Data and Clock are fed in on the SDA and SCL lines
respectively as defined by
can either accept data (write mode), or send data (read
mode). The LSB of the address byte (R/W) sets the
device into write mode if it is low, and read mode if it is
high. Table 2 illustrates the format of the data. The
device can be programmed to respond to several
addresses, which enables the use of more than one
synthesiser in an I
address is selected by applying a voltage to the ‘address’
input.
Units
Vpp
mW
C/W
C/W
o
o
kV
V
V
V
C
C
2
C data generated from nominal 3.3V and 5V
2
Transient
Differential
All ports off
mil std 883 latest revision method 3015
class 1
C logic level is selected by the bi-directional
2
C bus system. Table 3 shows how the
Conditions
I
2
C bus format. The synthesiser
2
C data bus and is
5