alc880 Realtek Semiconductor Corporation, alc880 Datasheet - Page 27

• Manufacturer Part Number: alc880
• Description: 7.1 Channel High Definition Audio Codec
• Manufacturer: Realtek Semiconductor Corporation

Enter ‘Link Reset’:
Exit from ‘Link Reset’:
7.1 Channel High Definition Audio Codec
BCLK
SYNC
SDOs
SDIs
RST#
Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
As the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the
The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state
All link signals driven by controller and codecs should be tri-state by internal pull low resistors
If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
Software is responsible for de-asserting RST# after a minimum of 100µs BCLK running time (the
Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
link reset
end of the frame
100µsec provides time for the codec PLL to stabilize)
last bit of frame SYNC)
1
2
Previous Frame
SYNC is absent
Normal Frame
3
Driven Low
Driven Low
Driven Low
4 BCLK
Figure 13. Link Reset Timing
4
4 BCLK
17
5
Pulled Low
Pulled Low
Pulled Low
Pulled Low
Link in Reset
6
>=100 usec
Track ID: JATR-1076-21
7
>= 4 BCLK
Wake Event
8
ALC880 Series
Initialization Sequence
Normal Frame
SYNC
Datasheet
9
Rev. 1.4