ISL12022 INTERSIL [Intersil Corporation], ISL12022 Datasheet - Page 11

• Manufacturer Part Number: ISL12022
• Manufacturer: INTERSIL [Intersil Corporation]

ADDR. SECTION
the crystal. Initial values are preset and recalled on initial
power-up for the Initial AT and DT settings (IATR, IDTR),
temperature coefficient (ALPHA), crystal capacitance
(BETA), and the crystal turn-over temperature (XTO). These
initial values are typical of units available on the market,
although the user may program specific values after testing
for best accuracy. The function can be enabled/disabled at
any time and can be used in battery mode as well.
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101111x” and reads or writes to addresses
[00h:2Fh]. The defined addresses and default values are
described in the Table 1. The battery backed general
purpose SRAM has a different slave address (1010111x), so
it is not possible to read/write that section of memory while
accessing the registers.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 8 sections. They are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (9 bytes): Address 07h to 0Fh.
3. Alarm (6 bytes): Address 10h to 15h.
4. Time Stamp for Battery Status (5 bytes): Address 16h to
5. Time Stamp for V
0Ah
0Bh
0Ch
0Dh
0Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
1Ah.
1Fh.
CSR
RTC
PWR_VBAT
PWR_VDD
NAME
ALPHA
REG
FDTR
BETA
FATR
ITRO
MO
DW
INT
DD
SC
MN
HR
YR
SR
DT
Status (5 bytes): Address 1Bh to
11
IDTR01
CLRTS
BUSY
ARST
YR23
TSE
MIL
D
0
0
0
0
0
0
0
7
RESEALB
ALPHA6
IDTR00
WRTC
OSCF
MN22
BTSE
SC22
YR22
D
6
0
0
0
0
0
0
TABLE 1. REGISTER MEMORY MAP
VB85Tp2
DSTADJ
ALPHA5
FFATR5
IATR05
SC21
MN21
HR21
YR21
BTSR
DT21
IM
D
5
0
0
0
ISL12022
VB85Tp1
FOBATB
ALPHA4
IATR04
FDTR4
BETA4
FATR4
MN20
MO20
SC20
HR20
YR20
DT20
ALM
4
D
0
BIT
10. Crystal ALPHA at high temperature, ALPHA_H (1 byte):
11. Scratch Pad (2 bytes): Address 2Eh and 2Fh
Write capability is allowable into the RTC registers (00h to
06h) only when the WRTC bit (bit 6 of address 08h) is set to
“1”. A multi-byte read or write operation should be limited to
one section per operation for best RTC time keeping
performance.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC and Alarm registers, the read
instruction latches all clock registers into a buffer, so an
update of the clock does not change the time being read. At
the end of a read, the master supplies a stop condition to
end the operation and free the bus. After a read, the address
remains at the previous address +1 so the user can execute
a current address read and continue reading the next
register. When the previous address is 2Fh, the next
address will wrap around to 00h.
It is not necessary to set the WRTC bit prior to writing into
the control and status, alarm, and user SRAM registers.
VB85Tp0
6. Daylight Savings Time (8 bytes): 20h to 27h.
7. TEMP (2 bytes): 28h to 29h
8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh
9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch
ALPHA3
IATR03
FDTR3
BETA3
FATR3
MN13
MO13
SC13
HR13
DT13
YR13
LVDD
FO3
3
D
0
2Dh
V
VB75Tp2
ALPHA2
LBAT85
IATR02
FDTR2
BETA2
FATR2
DD
MN12
MO12
SC12
HR12
DT12
YR12
DW2
FO2
2
Trip2
V
VB75Tp1
ALPHA1
LBAT75
IATR01
FDTR1
BETA1
FATR1
DD
MN11
MO11
SC11
HR11
YR11
DT11
DW1
FO1
1
Trip1
V
VB75Tp0
ALPHA0
IATR00
BETA0
FDTR0
FATR0
DD
MN10
HR10
MO10
RTCF
SC10
DT10
YR10
DW0
FO0
0
Trip0
RANGE
0 to 59
0 to 59
0 to 23
1 to 31
1 to 12
0 to 99
0 to 6
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
June 23, 2009
DEFAULT
FN6659.2
00h
00h
00h
01h
01h
00h
00h
01h
01h
00h
00h
20h
46h
00h
00h
00h