SDA5252 SIEMENS [Siemens Semiconductor Group], SDA5252 Datasheet - Page 73

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SDA5252

Manufacturer Part Number
SDA5252
Description
TVTEXT 8-Bit Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet

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Interrupt Control Register
Default after reset: XXXX0101
EX1R
EX1F
EX0R
EX0F
– Transition-Activated Interrupts
The IE0, IE1 flags are set by a transition at INT0, INT1, respectively; they are cleared
during entering the corresponding interrupt service routine.
For transition-activated operation, the input must remain active for more than six
oscillator periods, but needs not to be synchronous with the oscillator. The opposite
transition of a transition-activated input may occur at any time after the six oscillator
period latching time, but the input must remain inactive for six oscillator periods before
reactivation.
– Level-Activated Interrupts
The IE0, IE1 flags are set whenever INT0, INT1 are respectively sampled at low level.
Sampling INT0, INT1 at high level clears IE0, IE1, respectively.
For level-activated operation, if the input is active during the sampling that occurs seven
oscillator periods before the end of the instruction in progress, an interrupt subroutine
call is made. The level-activated input needs to be low only during the sampling that
occurs seven oscillator periods before the end of the instruction in progress and may
remain low during the entire execution of the service program. However, the input must
be deactivated before the service routine is completed to avoid invoking a second
interrupt, or else another interrupt will be generated.
Extension of Standard 8051 Interrupt Logic
For more flexibility, the SDA 525x family provides a new feature in detection EX0 and
EX1 in edge-triggered mode. Now there is the possibility to trigger an interrupt on the
falling and / or rising edge at the dedicated Port3-Pin. Therefore, an additional register
IRCON has been defined, which is described on the top.
Semiconductor Group
(MSB)
(IT0 = 1, IT1 = 1)
(IT0 = 0, IT1 = 0)
if set, EX1-interrupt detection on rising edge at Pin P3.3
if set, EX1-interrupt detection on falling edge at Pin P3.3
if set, EX0-interrupt detection on rising edge at Pin P3.2
if set, EX0-interrupt detection on falling edge at Pin P3.2
B
IRCON
73
EX1R
EX1F
SFR-Address AB
EX0R
SDA 525x
1998-04-08
(LSB)
EX0F
H

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