MB15E06PFV1 FUJITSU [Fujitsu Component Limited.], MB15E06PFV1 Datasheet - Page 10

• Manufacturer Part Number: MB15E06PFV1
• Description: Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz Prescaler
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

10
MB15E06
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
3. Power Saving Mode (Intermittent Mode Control Circuit)
Note :
Setting a PS pin to Low, the IC enters into power saving mode resultatly current sonsumption can be limited to
10 A (max.) . Setting PS pin to High, power saving mode is released so that the IC works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from the power
saving mode. In general, the power consumption can be saved by the intermittent operation that powering down
or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator
output signal is unpredictable due to an undefined phase relation between reference frequency (f
ison frequency (f
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector
during power up, thus keeping the loop locked.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10 A (max.) .
* : When the LPF and VCO characteristics are
* : When the VCO characteristics are similar to
(1) PS
(2) Set serial data 1 s later after power supply remains stable (V
(3) Release power saving mode (PS : L
similar to (1) , set FC bit high.
(2) , set FC bit low.
While the power saving mode is executed, ZC pin should be set at “H” or open. If ZC is set at “L”
PS pin must be set “L” at Power-ON.
The power saving mode can be released (PS : L
During the power saving mode, it is possible to input the serial data.
during power saving mode, approximately 10 A current flows.
L (power saving mode) at Power ON
p
) and may in the worst case take longer time for lock up of the loop.
V
Clock
Data
LE
PS
CC
OFF
(1)
H) 100 ns later after setting serial data.
t
V
Fr equen cy
1 s
Outpu t
H i gh
V C O
ON
(2)
H) 1 s later after power supply remains stable.
LP F Ou tp ut V ol t ag e
CC
t
PS
2.2 V) .
(3)
100 ns
La rg e
r
) and compar-
( 1)
( 2)