P10C68- ZARLINK [Zarlink Semiconductor Inc], P10C68- Datasheet - Page 5

• Manufacturer Part Number: P10C68-
• Description: CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

SRAM MEMORY OPERATION
READ CYCLES 1 AND 2 (See note 8)
NOTES
8.
9.
10.
11.
12.
Standard
t
t
t
t
ELICCH
EHICCL
t
t
t
t
t
t
t
t
WHQV
Test conditions (unless otherwise stated):
Commercial and Industrial Temperature Range
AVQV
GLQV
AXQX
EHQZ
GLQX
GHQZ
ELQV
AVAV
ELQX
DQ (DATA OUT)
Tamb = -40°C to + 85°C, Vcc = + 5V ± 10%
E (bar), G (bar) and W (bar) must make the transition between VIH(min) to VIL(max), or VIL(max) to VIH(min) in a
monotonic fashion. NE (bar) must be ≥ VIH during entire cycle.
For READ CYCLE 1 and 2, W (bar) and NE (bar) must be high for entire cycle.
Device is continuously selected with E (bar) low, and G (bar) low.
Measured ±200mV from steady state output voltage. Load capacitance is 5pF.
Parameter guaranteed but not tested.
ADDRESS
Symbol
W
Alternative
t
t
t
t
ACS
t
t
t
OHZ
t
OLZ
t
t
t
t
WR
RC
OE
OH
AA
HZ
PA
PS
LZ
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Outout disable to output inactive
Chip enable to power active
Chip disable to power standby
Write recovery time
t
t
WHQV
AXQX
Parameter
t
Min.
t
AVQV
AVAV
35
P10C68-35
P11C68-35
5
5
0
0
Max.
35
35
20
20
15
25
45
Min.
45
P10C68-45
P11C68-45
5
5
0
0
Max.
45
45
25
25
20
25
55
DATA VALID
P10C68/P11C68
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
10
11
11
12
12
9
5