CM3202-00SM CALMIRCO [California Micro Devices Corp], CM3202-00SM Datasheet - Page 8

• Manufacturer Part Number: CM3202-00SM
• Description: DDR VDDQ and Termination Voltage Regulator
• Manufacturer: CALMIRCO [California Micro Devices Corp]

Application Info (cont’d)
Figure 1. Typical DDR terminations, Class II
The V
ber of data lines and the resistance of the termination
resistor, but does not vary with memory size. In a typi-
cal DDR data bus system each data line termination
may momentarily consume 16.2-mA to achieve the
405-mV minimum over V
A typical 64 Mbyte SSTL-2 memory system, with 128
terminated lines, has a worst-case maximum V
ply current up to ± 2.07A. However, a DDR memory
system is dynamic, and the theoretical peak currents
only occur for short durations, if they ever occur at all.
These high current peaks can be handled by the V
external capacitor. In a real memory system, the con-
tinuous average V
is less than ± 200 mA.
The V
rent to the memory banks, could also supply current to
controllers and other circuitry. The current level typi-
cally stays within a range of 0.5A to 1A, with peaks up
to 2A or more, depending on memory size and the
computing operations being performed.
The tight tracking requirements and the need for V
sink, as well as source, current provide unique chal-
lenges for powering DDR SDRAM.
CM3202 Regulator
The CM3202 dual output linear regulator provides all of
the power requirements of DDR memory by combining
two linear regulators into a single TDFN-8 or SOIC-8
package. V
© 2006 California Micro Devices Corp. All rights reserved.
8
I
terminaton
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
VDDQ
TT
DDQ
Transmitter
power requirement is proportional to the num-
=
power supply, in addition to supplying cur-
DDQ
Rs = 25
--------------------- -
Rt 25Ω
405mV
(
regulator can supply up to 2A current,
TT
)
current level in normal operation
=
Line
16.2mA
TT
VREF (=VDDQ/2)
VTT (=VDDQ/2)
needed at the receiver:
Rt = 25
VDDQ
l
Receiver
TT
Tel: [phone]
TT
sup-
TT
to
and the two-quadrant V
current sink and source capability to ±2A. The V
linear regulator uses a PMOS pass element for a very
low dropout voltage, typically 500mV at a 2A output.
The output voltage of V
voltage divider. The second output, V
V
tor can source, as well as sink, up to 2A current. The
CM3202 is designed for optimal operation from a nom-
inal 3.3VDC bus, but can work with VIN as high as 5V.
When operating at higher VIN voltages, attention must
be given to the increased package power dissipation
and proportionally increased heat generation.
V
such as a comparator, with little current draw. An ade-
quate V
divider of precision, matched resistors from V
ground. A small ceramic bypass capacitor can also be
added for improved noise performance.
Input and Output Capacitors
The CM3202 requires that at least a 220
capacitor be located near the V
maintain the input bus voltage during load transients.
An additional 4.7
and the GND, located as close as possible to those
pins, is recommended to ensure stability.
A minimum of a 220μF electrolytic capacitor is recom-
mended for the V
ceramic capacitor between the V
very close to those pins, is recommended.
A minimum of a 220
mended for the V
low ESR to achieve best output transient response. SP
or OSCON capacitors provide low ESR at high fre-
quency, and thus are a good choice. In addition, place
a 4.7
GND, located very close to those pins. The total ESR
must be low enough to keep the transient within the
V
sink. An average current step of ± 0.5A requires:
Both outputs will remain stable and in regulation even
during light or no load conditions.
DDQ
REF
TT
ESR
window of 40mV during the transition for source to
μ
/2 by an internal resistor divider. The V
is typically routed to inputs with high impedance,
l
<
F ceramic capacitor between the V
40mV
-------------- -
REF
Fax: [phone]
1A
can be created with a simple voltage
=
μ
40mΩ
TT
F ceramic capacitor between the V
DDQ
μ
output. This capacitor should have
F, electrolytic capacitor is recom-
DDQ
TT
output. An additional 4.7μF
l
termination regulator has
can be set by an external
www.cmd.com
IN
DDQ
PRELIMINARY
pin for stability and to
and GND, located
TT
, is regulated at
μ
CM3202
F electrolytic
TT
TT
pin and
regula-
DDQ
05/08/06
DDQ
to
IN