lc89977m Sanyo Semiconductor Corporation, lc89977m Datasheet

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lc89977m

Manufacturer Part Number
lc89977m
Description
Ccd Delay Line For Pal
Manufacturer
Sanyo Semiconductor Corporation
Datasheet

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Ordering number : EN5545
Preliminary
Overview
The LC89977M is CCD delay line for PAL television
system that includes a chrominance signal crosstalk
exclusion filter and a luminance signal 1-H delay line on
chip.
Features
• 5-V single-voltage power supply
• Built-in 3
• Can be switched between the PAL/GBI, and 4.43NTSC
• Includes a built-in crosstalk exclusion comb filter for the
• Peripheral circuits provided on chip for operation with a
• Positive-phase signal input, positive-phase signal output
Functions
• CCD shift registers (for chrominance and luminance
• Timig generator and clock driver for CCD
• Delay time selective circuit
• CCD signal adder
• Auto-bias circuit
• Sync tip clamp circuit (luminance signal)
• Center bias circuit (chrominance signal)
• Sample-and-hold circuit
• 3 PLL frequency multiplier circuit
• 3fsc clock output circuit
• High voltage generator for CCD Reset Drain (RD)
Specifications
Absolute Maximum Ratings at Ta = 25°C
Supply voltage
Allowable power dissipation
Operating temperature
Storage temperature
operation from an fsc (4.43 MHz) input.
formats by setting control pin values.
chrominance signal that provides high-precision comb
characteristics in an adjustment-free circuit.
minimum of external components.
(luminance signal)
signals)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
PLL frequency multiplier circuit allows 3fsc
Parameter
Symbol
Pd max
Topr
Tstg
V
DD
Package Dimensions
unit: mm
3111-MFP14S
Conditions
CCD Delay Line for PAL
[LC89977M]
N3096HA(OT) No. 5545-1/7
LC89977M
–0.3 to +6.0
–55 to +125
–10 to +60
Ratings
SANYO: MFP14S
250
MOS LSI
Unit
mW
°C
°C
V

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lc89977m Summary of contents

Page 1

... Ordering number : EN5545 Preliminary Overview The LC89977M is CCD delay line for PAL television system that includes a chrominance signal crosstalk exclusion filter and a luminance signal 1-H delay line on chip. Features • 5-V single-voltage power supply • Built-in 3 PLL frequency multiplier circuit allows 3fsc operation from an fsc (4.43 MHz) input. ...

Page 2

... Allowable Operating Ranges 25°C Parameter Supply voltage Clock input amplitude Clock frequency Chrominance signal input amplitude Luminance signal input amplitude Pin Assignment Block Diagram LC89977M Symbol Conditions CLK F Sine wave CLK V IN-C V IN-Y Ratings Unit min typ max 4.75 5.00 5.25 V 300 500 ...

Page 3

... Parameter Supply current [Chrominance signal characteristics] (with no input to Y-IN) DC output voltage Voltage gain Comb depth Linearity Clock leakage (3fsc) Clock leakage (fsc) Noise Output impedance 0-H delay time LC89977M 2H (1703. (1) 1H (845. (1) Symbol Conditions 4.43361875 MHz, V CLK Switch states ...

Page 4

... D The C-OUT output for an fa input [mVp-p] Test Frequencies 4.429662 MHz D 4.425694 MHz D-2 LC89977M Switch states Symbol SW1 SW2 SW3 Test conditions ...

Page 5

... Apply a 5-step staircase wave (as in the figure below) to Y-IN, and measure the differential gain and differential phase in the Y-OUT output using a vector scope. LC89977M The output for a 200-mVp-p input [mVp-p] —————————————————— [dB] ...

Page 6

... V2 be the Y-OUT output when SW3 is set to the ‘b’ position. V2 [mVp-p] – V1 [mVp- ———————————— [mVp-p] 18. Measure the delay time in the Y-OUT output with respect to the input to Y-IN. LC89977M 500 [ ] No. 5545-6/7 ...

Page 7

... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1997. Specifications and information herein are subject to change without notice. LC89977M No. 5545-7/7 ...

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