adc-hz-883 C&D Technologies., adc-hz-883 Datasheet - Page 3

• Manufacturer Part Number: adc-hz-883
• Description: 12-bit, 8 And 20?sec Analog-to-digital Converters
• Manufacturer: C&D Technologies.

5. Note that output coding is complementary coding. For
6. These converters can be operated with an external clock.
0 to +10V
+9.9976V
+8.7500
+7.5000
+5.0000
+2.5000
+1.2500
+0.0024
0.0000
unipolar operation it is complementary binary, and for
bipolar operation it is complementary offset binary or
complementary two’s complement. In cases in which
bipolar coding of offset binary or two’s complement is
required, this can be achieved by inverting the analog input
to the converter (using an op amp connected for gain of –1).
The converter is then calibrated so that –FS analog input
gives an output code of 0000 0000 0000, and +FS – 1LSB
gives 1111 1111 1111.
To accomplish this, a negative pulse train is applied to
START CONVERT (pin 21). The rate of the external clock
must be lower than the rate of the internal clock as adjusted
(see Short Cycle Operation tables) for the converter
resolution selected. The pulse width of the external clock
®
INPUT RANGE
TO SELECTED
DATA OUTPUT PIN
UNIPOLAR OPERATION
+4.9988V
+4.3750
+3.7500
+2.5000
+1.2500
+0.6250
+0.0012
CODING TABLE
0 to +5V
0.0000
VOLTAGE
PIN 17
+15V
SHORT
CYCLE
+5V
0V
16
15
14
CLOCK RATE VS. VOLTAGE
CONNECTIONS
BINARY CODING
MSB
0000 0000 0000
0001 1111 1111
0011 1111 1111
0111 1111 1111
1011 1111 1111
1101 1111 1111
1111 1111 1110
1111 1111 1111
ADC-HX
600kHZ
720kHZ
880kHz
®
COMP.
Refer to Technical Note 4 for methods of reducing the ADC-HX or ADC-HZ conversion times.
CLOCK RATE
CLOCK
RATE
LSB
17
ADC-HZ
1.5MHZ
1.8MHz
2.2MHz
–10.0000
+9.9951V
+7.5000
+5.0000
–5.0000
–7.5000
–9.9951
0.0000
±10V
+5V
+15V
SHORT CYCLE OPERATION
INPUT VOLTAGE RANGE
+4.9976V
+3.7500
+2.5000
–2.5000
–3.7500
–4.9976
–5.0000
0.0000
±5V
7. When the input buffer amplifier is used, a delay equal to its
should be between 100 and 300 nanoseconds. Each N-bit
conversion cycle requires a pulse train of N + 1 clock pulses
for completion, e.g., an 8-bit conversion requires 9 clock
pulses for completion. A continuous pulse train may be
used for consecutive conversions, resulting in an N-bit
conversion every N + 1 pulses, or the E.O.C. output may be
used to gate a continuous pulse train for single conversions.
settling time must be allowed between the input level change,
such as a multiplexer channel change, and the negative-
going edge of the START CONVERT pulse. If the buffer is
not required, BUFFER INPUT (pin 30) should be tied to
ANALOG COMMON (pin 26). This prevents the unused
amplifier from introducing noise into the converter. For
applications not using the buffer, the converter must be driven
from a source with an extremely low output impedance.
RES. (BITS)
RESOLUTION
ADC-HX Conversion Time
ADC-HZ Conversion Time
Connect These
Pins Together
+2.4988V
+1.8750
+1.2500
–1.2500
–1.8750
–2.4988
–2.5000
BIPOLAR OPERATION
1
2
3
4
5
6
0.0000
±2.5V
CODING TABLE
8, 10 & 12-BIT CONVERSION TIMES
PIN 14 TO
PIN 11
PIN 10
PIN 9
PIN 8
PIN 7
PIN 6
PIN 14 CONNECTION
OFFSET BINARY
MSB
0000 0000 0000
0111 1111 1111
0001 1111 1111
0011 1111 1111
1011 1111 1111
1101 1111 1111
1111 1111 1110
1111 1111 1111
COMP.
12 BITS
ADC-HX, ADC-HZ
17 & 15
14 & 16
20µs
RES. (BITS)
8µs
LSB
Analog-to-Digital Converters
10
11
12
7
8
9
10 BITS
17 & 16
14 & 2
15µs
6µs
1000 0000 0000
MSB
1001 1111 1111
1011 1111 1111
1111 1111 1111
0011 1111 1111
0101 1111 1111
0111 1111 1110
0111 1111 1111
COMPLEMENT
COMP. TWO’S
PIN 14 TO
PIN 5
PIN 4
PIN 3
PIN 2
PIN 1
PIN 16
17 & 28
8 BITS
14 & 4
10µs
4µs
LSB