gvt71256f18 ETC-unknow, gvt71256f18 Datasheet

gvt71256f18

Manufacturer Part Number

gvt71256f18

Description

256k Synchronous Burst Sram

Manufacturer

ETC-unknow

Datasheet

1.GVT71256F18.pdf (13 pages)

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FEATURES

• Fast access times: 3.5, 3.8, and 4.0ns

• Fast clock speed: 166, 150, 133, and 117MHz

• Provide high performance 3-1-1-1 access rate

• Fast OE# access times: 3.5ns and 3.8ns

• Optimal for performance (two cycle chip deselect, depth

• 3.3V -5% and +10% core power supply

• 2.5V or 3.3V I/O supply

• 5V tolerant inputs except I/O’s

• Clamp diodes to VSSQ at all inputs and outputs

• Common data inputs and data outputs

• BYTE WRITE ENABLE and GLOBAL WRITE control

• Three chip enables for depth expansion and address

• Address, data and control registers

• Internally self-timed WRITE CYCLE

• Burst control pins (interleaved or linear burst sequence)

• Automatic power-down for portable applications

• High density, high speed packages

OPTIONS

• Timing

• Packages

Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051

Tel (408) 566-0688

Rev. 2/7/98

GALVANTECH

BURST SRAM

PIPELINED OUTPUT

SYNCHRONOUS

expansion without wait state)

pipeline

3.5ns access/6.0ns cycle

3.8ns access/6.7ns cycle

4.0ns access/7.5ns cycle

4.0ns access/8.5ns cycle

100-pin TQFP

Fax (408) 566-0699

MARKING

-3

-4

-5

-6

, INC.

256K X 18 SYNCHRONOUS BURST SRAM

GENERAL DESCRIPTION

employs high-speed, low power CMOS designs using

advanced

technology. Each memory cell consists of four transistors and

two high valued resistors.

SRAM cells with advanced synchronous peripheral circuitry

and a 2-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered clock input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

chip enable (CE#), depth-expansion chip enables (CE2# and

CE2), burst control inputs (ADSC#, ADSP#, and ADV#),

write enables (WEL#, WEH#, and BWE#), and global write

(GW#).

and burst mode control (MODE). The data outputs (Q),

enabled by OE#, are also asynchronous.

address status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can be

internally generated as controlled by the burst advance pin

(ADV#).

chip to initiate self-timed WRITE cycle. WRITE cycles can

be one to four bytes wide as controlled by the write control

inputs. Individual byte write allows individual byte to be

written. WEL# controls DQ1-DQ8 and DQP1. WEH#

controls DQ9-DQ16 and DQP2. WEL#, and WEH# can be

active only with BWE# being LOW. GW# being LOW causes

all bytes to be written. WRITE pass-through capability allows

written data available at the output for the immediately next

READ cycle. This device also incorporates pipelined enable

circuit for easy depth expansion without penalizing system

performance.

supply and all outputs operate on a +2.5V supply. All inputs

and outputs are JEDEC standard JESD8-5 compatible. The

device is ideally suited for 486, Pentium

PowerPC

wide synchronous data bus.

The Galvantech Synchronous Burst SRAM family

The GVT71256F18 SRAM integrates 262,144x18

Asynchronous inputs include the output enable (OE#)

Addresses and chip enables are registered with either

Address, data inputs, and write controls are registered on-

The GVT71256F18 operates from a +3.3V core power

256K x 18 SRAM

+3.3V CORE SUPPLY, +2.5V I/O SUPPLY

FULLY REGISTERED, BURST COUNTER

systems and for systems that are benefited from a

triple-layer

polysilicon,

GVT71256F18

PowerPC is a trademark of IBM Corporation.

Pentium is a trademark of Intel Corporation.

Galvantech, Inc. reserves the right to change

double-layer

products or specifications without notice.

, 680x0, and

metal

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gvt71256f18 Summary of contents

Page 1

... READ cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. The GVT71256F18 operates from a +3.3V core power supply and all outputs operate on a +2.5V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. The device is ideally suited for 486, Pentium ...

Page 2

... X 18 SYNCHRONOUS BURST SRAM UPPER BYTE WRITE D Q LOWER BYTE WRITE D Q ENABLE Input Register Address Register CLR Binary Counter & Logic 2 GVT71256F18 Q OUTPUT REGISTER DQ1- DQ16 DQP1, DQP2 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 3

... CE# Input- Chip Enable: This active LOW input is used to enable the device and to gate ADSP#. Synchronous CE2# Input- Chip Enable: This active LOW input is used to enable the device. Synchronous 3 GVT71256F18 A10 ...

Page 4

... No Connect: These signals are not internally connected. Third Address Fourth Address (internal) (internal) A...A10 A...A11 A...A11 A...A10 A...A00 A...A01 A...A01 A...A00 Third Address Fourth Address (internal) (internal) A...A10 A...A11 A...A11 A...A00 A...A00 A...A01 A...A01 A...A10 4 GVT71256F18 DESCRIPTION Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 5

... BWE# WEH# WEL GVT71256F18 ADV# WRITE# OE# CLK L-H High L-H High L-H High L-H High L-H High L L-H High-Z ...

Page 6

... < VCC IL OUT VCC VCCQ SYM TYP or > Icc 150 SB2 SB3 I 40 SB4 ; VCC = MAX GVT71256F18 MIN MAX UNITS NOTES 1.7 VCC+0.3 V 1.7 4.6 V -0.3 0 1.7 V 0.7 V 3.135 3.6 V 2.375 VCC UNITS NOTES ...

Page 7

... MHz C I VCC = 3. CONDITIONS SYMBOL TQFP TYP Still air, soldered on 4. 1.125 inch 4-layer PCB JC OUTPUT LOW VOLTAGE m ax VOL (V) -105 -0.5 -105 0 -105 0.4 -83 0.8 -70 1.25 -30 1.6 -10 2.8 0 3.2 0 3.4 7 GVT71256F18 - 133MHz 117MHz MIN MAX MIN MAX UNITS 7.5 8.5 ns 2.8 3.4 ns 2.8 3.4 ns 4.0 4.0 ns 1.5 1 1.5 7.5 1.5 8.5 ns 3.8 3.8 ns ...

Page 8

... Capacitance derating applies to capacitance different from the load capacitance shown in Fig / increases with greater t KQHZ is less o C and 8.5ns cycle time. 8 GVT71256F18 1.25V Fig. 1 OUTPUT LOAD EQUIVALENT Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 9

... Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. February 7, 1998 Rev. 2/7/98 , INC. 256K X 18 SYNCHRONOUS BURST SRAM READ TIMING OEQ t OELZ Q(A1) Q(A2) Q(A2+1) SINGLE READ 9 GVT71256F18 t H Q(A2+2) Q(A2+3) Q(A2) BURST READ Galvantech, Inc. reserves the right to change products or specifications without notice. Q(A2+1) ...

Page 10

... Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. February 7, 1998 Rev. 2/7/98 , INC. 256K X 18 SYNCHRONOUS BURST SRAM WRITE TIMING OEHZ D(A1) D(A2) D(A2+1) D(A2+1) BURST WRITE 10 GVT71256F18 D(A2+2) D(A2+3) D(A3) D(A3+1) BURST WRITE Galvantech, Inc. reserves the right to change products or specifications without notice. D(A3+2) ...

Page 11

... Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. February 7, 1998 Rev. 2/7/98 , INC. 256K X 18 SYNCHRONOUS BURST SRAM READ/WRITE TIMING Q(A1) Q(A2) D(A3) Q(A3) Pass Through Single Write 11 GVT71256F18 A5 Q(A4) Q(A4+1) Q(A4+2) D(A5) D(A5+1) Burst Read Burst Write Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 12

... GALVANTECH 100 Pin TQFP Package Dimensions # 1 1.40 + 0.05 1.60 Max Note: All dimensions in Millimeters February 7, 1998 Rev. 2/7/98 , INC. 256K X 18 SYNCHRONOUS BURST SRAM 16.00 + 0.10 14.00 + 0.10 0.65 Basic 12 GVT71256F18 0.30 + 0.08 0.60 + 0.15 Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 13

... Part Number February 7, 1998 Rev. 2/7/98 , INC. 256K X 18 SYNCHRONOUS BURST SRAM 13 GVT71256F18 Speed (3 = 3.5ns access/6.0ns cycle 4 = 3.8ns access/6.7ns cycle 5 = 4.0ns access/7.5ns cycle 6 = 4.0ns access/8.5ns cycle) Package (T = 100 PINTQFP) Galvantech, Inc. reserves the right to change products or specifications without notice. ...

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