k6r1004c1d Samsung Semiconductor, Inc., k6r1004c1d Datasheet
k6r1004c1d
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k6r1004c1d Summary of contents
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... K6R1004C1D Document Title 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating). Revision History Rev. No. History Rev. 0.0 Initial release with Preliminary. Rev. 0.1 Current modify Rev. 0.2 1. Delete 15ns speed bin. 2. Change Icc for Industrial mode. Item 10ns I CC(Industrial) 12ns Rev. 1.0 1. Final datasheet release. ...
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... K6R1004C1D 1Mb Async. Fast SRAM Ordering Information Org. Part Number K6R1004C1D-J(K)C(I) 10 256K x4 K6R1004V1D-J(K)C(I) 08/10 K6R1008C1D-J(K,T,U)C(I) 10 128K x8 K6R1008V1D-J(K,T,U)C(I) 08/10 K6R1016C1D-J(K,T,U,E)C(I) 10 64K x16 K6R1016V1D-J(K,T,U,E)C(I) 08/10 VDD(V) Speed ( ns ) PKG 32-SOJ K: 32-SOJ(LF) 3.3 8/ 32-SOJ K : 32-SOJ(LF 32-TSOP2 3.3 8/ 32-TSOP2(LF 44-SOJ K : 44-SOJ(LF 44-TSOP2 3.3 8/ 44-TSOP2(LF 48-TBGA - 2 - PRELIMINARY PRELIMINARY CMOS SRAM Temp. & ...
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... The device is fabricated using SAM- SUNG′s advanced CMOS process and designed for high- speed circuit technology particularly well suited for use in high-density high-speed K6R1004C1D is packaged in a 400 mil 32-pin plastic SOJ. PIN CONFIGURATION N ...
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... K6R1004C1D ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature Commercial Industrial * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... Chip Selection to Power Up Time t PU Chip Selection to Power DownTime The above parameters are also guaranteed at industrial temperature range. =5.0V±10%, unless otherwise noted.) CC Output Loads(B) for 50Ω 1.5V L 30pF* K6R1004C1D-10 Min PRELIMINARY PRELIMINARY CMOS SRAM Value 3ns 1 ...
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... Data out High Current SB K6R1004C1D-10 Min Max ...
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... K6R1004C1D NOTES(READ CYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced ...
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... K6R1004C1D TIMING WAVEFORM OF WRITE CYCLE(3) Address ...
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... K6R1004C1D PACKAGE DIMENSIONS 32-SOJ-400 #32 11.18 ±0.12 0.440 ±0.005 #1 +0.10 0.43 -0.05 0. +0.004 0.017 0.0375 -0.002 #17 #16 21.36 MAX 0.841 20.95 ±0.12 0.825 ±0.005 1.30 ( 0.051 1.30 ( 0.051 +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 - 9 - PRELIMINARY PRELIMINARY CMOS SRAM Units:millimeters/Inches 9.40 ±0.25 0.370 ±0.010 +0.10 0.20 -0.05 +0.004 0.008 -0.002 0.69 MIN 0.027 ) 0.10 3.76 MAX MAX ...