w27e02 ETC-unknow, w27e02 Datasheet - Page 2

• Manufacturer Part Number: w27e02
• Manufacturer: ETC-unknow

6. FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27E02 has two control functions and both of these produce data at
the outputs.
#CE is for power control and chip select. #OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (T
(T
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an
hour), the W27E02 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an
EPROM writer with a special erase algorithm.
There are two ways to enter Erase mode. One is to raise V
#OE high, A9 = V
starts the erase operation. The other way is somewhat like flash, by programming two consecutive
commands into the device and then enter Erase mode. The two commands are loading Data = AA(hex)
to Addr. = 5555(hex) and Data = 10(hex) to Addr. = 2AAA(hex). Be careful to note that the #PGM pulse
widths of these two commands are different: One is 100 S, while the other is 100 mS. Please refer to
the Smart Erase Algorithm 1 & 2.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if V
#PGM high
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when V
V
equal the desired inputs. Pulsing #PGM low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully programmed
with the desired data or not. Hence, after each byte is programmed, a program verify operation should
be performed. The program verify mode automatically ensures a substantial program margin. This mode
will be entered after the program operation if V
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When #CE high, erasing or programming of non-target chips is inhibited, so that except for the
#CE, the W27E02 may have common inputs.
DD
CE
), and data are available at the outputs T
= V
CP
(5.0V ), #CE low, #OE high, the address pins equal the desired addresses, and the input pins
.
HH
(12V), and all other address pins are kept at fixed low or high. Pulsing #PGM low
OE
PP
after the falling edge of #OE, if T
= V
- 2 -
PP
(12V), #CE low, #OE low
ACC
PP
) is equal to the delay from #CE to output
to V
DD
PE
= V
Preliminary W27E02
(12V), V
PE
(5.0V ), #CE low, and #OE low,
DD
PP
= V
is raised to V
,
and #PGM high.
ACC
CE
(5.0V ), #CE low,
and T
CE
PP
timings
(12V),