hi-6121 Holt Integrated Circuits, Inc., hi-6121 Datasheet
hi-6121
Related parts for hi-6121
hi-6121 Summary of contents
Page 1
... The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a 100-pin plastic quad flat pack (PQFP). The HI-6121 has a 4-wire SPI (Serial Peripheral Interface) host connection and comes in a reduced pin count 52-pin PQFP or 64-pin QFN ...
Page 2
... BLOCK DIAGRAM HI-6120 MIL-STD-1553 Terminal With Host Bus Interface HI-6121 MIL-STD-1553 Terminal With Host SPI Interface LOCK EE1K AUTOEN EECOPY CONFIG. OPTION MTSTOFF LOGIC RTA4 - 0 RTAP BENDI BWID HI-6120 BTYPE ONLY WPOL STR or OE HOST BUS INTERFACE HI-6120 ...
Page 3
... Chip select output for the dedicated Serial Peripheral Interface (SPI) that connects to the optional external serial EEPROM used for automatic self-initialization. For this auto- initialization SPI, the device operates in SPI master mode while the external memory This SPI is separate from the host SPI found in the HI-6121. operates in slave mode. HOLT INTEGRATED CIRCUITS 3 pull-up resistor ...
Page 4
... BWID equals 0. When the HI-6120 is configured for 16-bit bus width, the BENDI input pin is “don’t care.” When using the HI-6121, this pin controls the byte order of the 16-bit data following the SPI command. ...
Page 5
... BTYPE INPUT INPUT STR or OE INPUT WAIT or WAIT OUTPUT WPOL INPUT THESE PINS APPLY TO HI-6121 ONLY PIN TYPE SO OUTPUT SI INPUT SCK INPUT . ACKINT INPUT (HI-6121PQx variant only) HI-6120, HI-6121 DESCRIPTION Tristate data bus for host read/write operations upon registers and shared RAM. ...
Page 6
... FUNCTIONAL OVERVIEW The Holt HI-6120 or HI-6121 provides a complete Remote Terminal (RT) interface between a host and a MIL-STD- 1553B dual redundant data bus. It automatically handles all aspects of the MIL-STD-1553 protocol, namely, encoding/decoding, message formatting, error checking, message data buffering, protocol checking, illegalization and default terminal responses. Internal static RAM is ...
Page 7
... A free-running 16-bit counter provides time-tag values that are recorded for each message transacted. The time-tag MEMORY AND REGISTER ADDRESSING The HI-6120 and HI-6121 have an internal address space of 32K 16-bit words. All memory addresses in this data sheet are expressed as hexadecimal numbers, using the C programming convention where the prefix “ ...
Page 8
... Words 0x0100 0x00FF Expanded at Right 0x0000 FIGURE 1. Address Mapping for Registers and RAM HI-6120, HI-6121 A ddresses in the range 0x0020 to 0x7FFF apply to static RAM memory. All RAM is read-write read by either the host or the internal device logic. he Some memory locations (specifically Descriptor Table Control Words) contain bits updated by both host and device ...
Page 9
... REGISTERS Residing at the start of the memory address space, 32 addresses are reserved for HI-6120 and HI-6121 registers. Register addresses overlay the shared RAM address space, but are separate from the shared dual-port RAM. All register bits are active high. Unless otherwise indicated, all registers are reset in software to the logic zero condition after Master Reset (except any bits reflecting the state of input pins) ...
Page 10
... This bit applies only to the following undefined mode code commands: If this bit is low (default state after valid, and RT response is based on individual mode command settings in the Illegalization Table HI-6120, HI-6121 and receiver (complete ”bus shutdown”). This is the recommended ...
Page 11
... SSRD8 Single-Strobe Read for 8-Bit Parallel Bus Mode. This bit only applies to HI-6120 (not HI-6121) and only applies when the parallel host bus is configured for 8-bit bus width. When performing 2-byte read accesses of external memory, some microprocessors with 8-bit bus assert individual Read Enable (or bytes ...
Page 12
... When the MCOPT4 bit equals zero, unique “bus select” values should be initialized by the host in the “Bus A Select” register (0x0012) and “Bus B Select” register (0x0013) for fulfillment of “selected HI-6120, HI-6121 master reset or (e) software reset by setting the SRST bit in Configuration Register 1. ...
Page 13
... If this bit is logic 0, reception of a “transmit vector word” mode command (MC16) causes automatic reset of the Service Request status bit. The Service Request bit is reset in the Status Word Bits HI-6120, HI-6121 The MCOPT4 bit in Configuration Register 2 is logic Inactive Bus Tx & Rx Status Word Disabled (Enabled) ...
Page 14
... When set, this read-only bit indicates the terminal is presently processing a message. This bit reflects the state of output pin ACTIVE and is cleared on reset. Note: Ths bit and the corresponding output pin are asserted upon valid command detection and negated when command processing is completed. HI-6120, HI-6121 (0x0002) After rising edge on the ...
Page 15
... This register contains the address for the descriptor table Control Word corresponding to the current command stored in the Current Command Register (0x0003). This register is updated 5us after the ACTIVE output is asserted. Bit 15 is MSB. Also see “Current Message Information Word Address” register, 0x000A. HI-6120, HI-6121 MCND MCRD 0 ...
Page 16
... Errors can be caused by Manchester encoding problems or protocol errors. The output is asserted and the Interrupt Log is updated. 9 —— Not used. 8 ILCMD Illegal Command Interrupt. If the ILCMD bit is set in the Interrupt Enable register, this bit is asserted each time an illegal message HI-6120, HI-6121 (0x0005 ...
Page 17
... SPIFAIL SPI Fail Interrupt (HI-6121 only). The HI-6121 uses a SPI interface for host access. The device operates in SPI Slave mode. If the SPIFAIL bit is set in the Interrupt Enable register, this bit is asserted each time an incorrect number of SCK clocks occurs during SPI chip select assertion, The Log is updated ...
Page 18
... If both MCOPT2 and MCOPT3 bits equal 0, the external host assumes responsibility for actions needed to perform “synchronize” duties upon reception of the valid MC17 “synchronize” command, but status transmission automatically occurs. HI-6120, HI-6121 pin Master Reset or SRST software reset. Reads to this register address MR ...
Page 19
... The contained value is a memory address used when fulfilling RAM or register read or write operations via the HI-6121 Serial Peripheral Interface (SPI). See data sheet section, ”Host Serial Peripheral Interface (SPI)” for further details. For HI-6120 devices, writes to this address have no effect; the address reads back 0x0000 if a host read cycle occurs. ...
Page 20
... Illegal Command Interrupt. Illegal commands are defined in the Illegalization Table. When enabled, the ILCMD interrupt is asserted when the Illegalization Table bit corresponding to the received command is logic 1. The Illegalization Table should only contain nonzero values when “illegal command detection” is being HI-6120, HI-6121 ...
Page 21
... Register” (below) and the section entitled “Illegalization Table” for further information. 7 SPIFAIL SPI Fail Interrupt (HI-6121 only). The HI-6121 uses a SPI interface for host access. The device operates in SPI Slave mode. When this bit is high, the number of SCK clocks occurs during SPI chip select assertion. 6-5 LBFA, LBFB Loopback Fail Bus A and Loopback Fail Bus B Interrupts ...
Page 22
... MC21 “shutdown override” without host assistance: If the mode command received was MC20, the Transmit Shutdown B bit in the built-in test (BIT) word is asserted. If mode command MC21 was received, the Transmit Shutdown B bit in the BIT Word is negated. Refer to Configuration Register 2 description of MCOPT4 bit for additional details. HI-6120, HI-6121 (0x0011) This register is cleared after ...
Page 23
... This bit is set when the Terminal Flag status bit is disabled while fulfilling an “inhibit terminal flag bit” mode code command (MC6). This bit is reset if terminal flag status bit disablement is later cancelled by an “override inhibit terminal flag bit” mode code command (MC7). HI-6120, HI-6121 (0x0014) memory test or auto-initialization failure occurred. This register is cleared by SRST ...
Page 24
... When this bit is asserted, RAM test failure is forced to verify that RAM BIST logic is functional. 13-11 RBSEL2-0 RAM BIST Select Bits 2-0. This 3-bit field selects the RAM BIST test mode applied when the RBSTART bit is set: RBSEL2:0 000 001 010 011 100 101 110 111 HI-6120, HI-6121 (0x0015 ...
Page 25
... LBALOG bit is low, digital loopback is selected and no data is transmitted onto the selected external MIL-STD-1553 bus. When the LBALOG bit is high, analog loopback is selected and a test word is transmitted onto and received from the selected external MIL-STD-1553 bus. HI-6120, HI-6121 a. Read and verify 0x0000 b. Write then read and verify 0x5555 c ...
Page 26
... Shown in Figure 2, each command word is comprised of a sync field, three 5-bit data fields, a single bit denoting Transmit / Receive with a parity bit. The hardware decoder uses the sync field to determine word type (command vs. data). Word validity HI-6120, HI-6121 (0x0018 ...
Page 27
... These commands must be transmitted with the T/ R bit is 0, the mode command is “undefined”. Twenty-two mode commands are “undefined mode HI-6120, HI-6121 Word Count Field * * Word Count field is replaced by Mode Code field when the SA field equals 0x00 or 0x1F Parity Bit commands ” ...
Page 28
... Mode commands that transmit or receive mode data words have a dedicated storage address range in shared RAM, eliminating the need for descriptor table data pointers. HI-6120, HI-6121 Each mode command with mode data word has its own fixed address for data storage ...
Page 29
... COMMAND ILLEGALIZATION TABLE The following pages describe various structures residing in the RAM shared between the host and HI-6120 or HI-6121 command processing logic. The host initializes these structures to control the terminal’s response to received commands. The first structure described is the command Illegalization Table used for “illegal command detection”. ...
Page 30
... For example, transmit commands to subaddress 1 are controlled by the words at 0x01C2 and 0x01C3. In Figure 4, these words are located in the “RT Address Transmit” HI-6120, HI-6121 block. The word stored at 0x01C3 controls subaddress 1 transmit commands having word counts 16 to 31. The word stored at 0x01C2 controls subaddress 1 transmit commands having word counts ...
Page 31
... Rx Subaddress 0 Block (mode codes) 0x0100 Illegalization Table Comprised of 32 2-Word Blocks per Quadrant FIGURE 4. Fixed Address Mapping for Illegalization Table HI-6120, HI-6121 RT Address Tx Mode Codes Address Tx Mode Codes Addr Tx SA30 Word Counts Addr Tx SA30 Word Counts Address Tx Mode Codes ...
Page 32
... Descriptor Table. When the TRXDB bit in Configuration Register 2 is negated temporary receive data buffer is disabled. At HI-6120, HI-6121 Bit No Status ...
Page 33
... EECKF Hardware 0 RAMIF Hardware HI-6120, HI-6121 More than one bit may be asserted in an Interrupt Identification Word. For example, IBR (interrupt broadcast received) and MERR (interrupt message error) can occur for the same message. One assertion of the output pin alerts the host when concurrent message interrupts occur ...
Page 34
... Interrupt Address Word 0x0041 INTERRUPT 1 0x0040 Interrupt Information Word FIGURE 8. Fixed Address Mapping for Interrupt Log Buffer HI-6120, HI-6121 The Interrupt Log Address Register points to this address after Interrupt 15 event occurs. Upon Interrupt 16 completion, device logic reinitializes the log address pointer to 0x0040 before Interrupt 17 is processed ...
Page 35
... All descriptor Control Words are initialized by the host (or auto-initialization) to define basic command response. HI-6120, HI-6121 Each Control Word specifies the data buffer method and host interrupt for a specific subaddress or mode command. Each subaddress has both a Receive Subaddress block and a Transmit Subaddress block ...
Page 36
... Subaddress 30 Block Receive Subaddress Quadrant. 32 Descriptor Blocks of 4 Words Each Subaddress 1 Block Subaddress 0 Block 0x0200 FIGURE 9. Address Mapping for Descriptor Table HI-6120, HI-6121 R R Example 4-Word Descriptor Blocks See Note. See Note. See Note. See Note. This figure assumes table base address = 0x0200. ...
Page 37
... IBRD asserted , and the interrupt is registered in the Interrupt Log. bit is high in Configuration Register 1. In this case, commands to RT address 31 are not recognized as valid by the device. HI-6120, HI-6121 Word Count Command WC4:0 Sync P Descriptor Address Format Depends On Command Word’ ...
Page 38
... The host asserts STOPP bit 3 to ask the device to temporarily disable ping-pong. Negating the STOPP bit asks the device to re-enable ping-pong. The device confirms ping-pong enable or disable state changes by writing the PPON bit. HI-6120, HI-6121 and the DPB bit does not toggle after message HOLT INTEGRATED CIRCUITS ...
Page 39
... MR master reset, SRST software reset or a host read cycle to this memory address. 10 DPB Data Pointer B. This status bit is maintained by the device and only applies in ping-pong buffer mode. This bit HI-6120, HI-6121 CIR2EN Don’t care master reset. Software reset (SRST) clears just the DBAC, DPB and ...
Page 40
... The PPEN, CIR1EN and CIR2EN bits are initialized by the host to select buffer mode. This table summarizes how buffer mode selection is encoded: PPEN HI-6120, HI-6121 sets this bit when a broadcast-transmit command is received for this subaddress. device indicates an illegal command was received. Terminal response varies, device CIR2EN Don’t care ...
Page 41
... If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables generation of an interrupt for mode code commands using indexed buffer mode when the INDX value decrements from Upon completion of command processing that results in INDX = 0, when IXEQZ interrupts HI-6120, HI-6121 MODE CODE COMMANDS use double (ping-pong) buffering or single (indexed) buffering.Single message ...
Page 42
... Each new message overwrites existing data in the buffer specified by DPB bit 10, and t he DPB bit does not toggle after command completion. 7-4 —— Not used. HI-6120, HI-6121 INTMES output pin is asserted, and the interrupt is registered in the Interrupt Log. This device acknowledges ping-pong is re-enabled by asserting HOLT INTEGRATED CIRCUITS ...
Page 43
... IWA Interrupt When Accessed. If the Interrupt Enable Register IWA bit is high, assertion of this bit enables interrupt generation at each instance of a valid mode code command. Upon completion of command processing, when IWA HI-6120, HI-6121 to re-enable ping-pong. The device confirms recognition of ping-pong enable ...
Page 44
... The device applies single-buffer index mode using Data Pointer A or Data Pointer B, per DPB bit 10. The DPB bit does not toggle after command completion. HI-6120, HI-6121 INTMES output pin is asserted, and the interrupt is registered in the Interrupt Log. This ...
Page 45
... Subaddress (non-mode) commands are transacted with one to 32 data words. These are stored in a data buffer in HI-6120, HI-6121 shared RAM. For receive commands, the device stores data received during message processing in the shared RAM buffer ...
Page 46
... NOTICE2 applies, all subaddresses using indexed or ping-pong modes must have an assigned 34-word broadcast data buffer in addition to the primary buffers listed above. Broadcast data segregation cannot be done using either circular buffer mode. HI-6120, HI-6121 Circular Buffer Mode 2. The number of messages transacted defines bulk transfer progress ...
Page 47
... This bit is asserted when the terminal responds to the receive command with BUSY status, due to global BUSY bit set in 1553 Status Bits Register, or command-specific MKBUSY bit set in the descriptor table Control Word. Received data words were buffered normally. HI-6120, HI-6121 Data Buffer Hex Address ...
Page 48
... Assertion of this bit indicates bus activity was detected immediately after the transmit command word, when a gap was expected. 12 WCTERR Word Count Error This bit is asserted if command is received with unexpected data word(s). HI-6120, HI-6121 the second command word, CW2 R Data Buffer Hex Address ...
Page 49
... However the device responds “in form” if illegal command detection is not used (corresponding bits in Illegalization Table are logic 0) For mode code commands without data, the data structure contains only the Message Information Word and Time-Tag Word. HI-6120, HI-6121 . Data Buffer ...
Page 50
... If this bit equals zero, message was transacted on Bus A. If bit equals one, it was transacted on Bus B. 4-0 MC4:0 Mode Code. This 5-bit field contains the mode code extracted from the command word. HI-6120, HI-6121 Data Buffer Hex Address Word Description 0x0500 Message Information Word ...
Page 51
... This bit is asserted if command is received with unexpected data word(s). 11 ---- Not used. 10 MERR Message Error. This bit is asserted when message error status change occurs during command processing. 12-13 for details. HI-6120, HI-6121 Data Buffer Hex Address Word Description > > 0x0500 Message Information Word 0x0501 ...
Page 52
... During ping-pong operation, the RT determines the active data buffer at the beginning of message processing. The Control Word DPB bit indicates the data pointer to be used HI-6120, HI-6121 by the next command. DPB equals logic 0 means Data Pointer A is used next; DPB equals logic 1 means Data Pointer B is used next ...
Page 53
... Message processing alternates between Data Buffers A and B. Upon successful message completion, the DPB bit in Descriptor Control Word is updated so next message uses other buffer. Buffers are overwritten every other message. Separate buffer for broadcast messages is optional. There is no alternate buffer for successive broadcast messages. HI-6120, HI-6121 Data Word 32 Data Words 2-31 ...
Page 54
... Message Information and Time-Tag Words for the assigned broadcast buffer, but no data is transmitted on the bus. Since broadcast-transmit is not allowed, multiple transmit subaddresses may share a HI-6120, HI-6121 common “bit bucket” broadcast buffer. A two word buffer is sufficient for storing the MIW and Time-Tag Word. Control ...
Page 55
... Message # broadcast command, while the other three messages are non-broadcast. Notice that the broadcast message does not affect DPB bit, but the following message resets BCAST bit. The interspersed broadcast command does not affect alternation between Buffer A and Buffer B. HI-6120, HI-6121 0x0565 0x0547 - 0x0564 ...
Page 56
... If decremented result is non-zero, Data Pointer A is adjusted so next message is stored above just-completed message. If decremented INDX is zero, Data Pointer A remains static, and IXEQZ interrupt occurs if enabled in Control Word. Figure 13. Illustration of Single-Buffer Indexed Mode HI-6120, HI-6121 If Descriptor Word 1 is stored at memory address N, Descriptor Word 2 is stored at address N+1, and the other two words are stored at addresses N+2 and N+3 ...
Page 57
... Each subaddress or mode command must have an assigned, valid non-zero broadcast buffer address. Non-broadcast message data is stored in Data Buffer A. HI-6120, HI-6121 There are two ways to deal with broadcast messages in indexed buffer mode: Option 1 for Index Mode Broadcast Messages: The first alternative isolates broadcast message information in the broadcast data buffer ...
Page 58
... INDEXED DATA BUFFERING, Cont. Messages #2, #3, etc Receive 4 Words Message #1 Receive 3 Words Increasing Memory Address Figure 14. Indexed Buffer Mode Example for a Receive Subaddress HI-6120, HI-6121 Data Word 4 0x050A 0x0509 Data Word 3 0x0508 Data Word 2 Data Word 1 0x0507 Time-Tag Word 2 0x0506 Msg Info Word 2 ...
Page 59
... EA value. Reserve 33 address locations past the EA address to accommodate a worst-case 32 data word message with a record starting at address = EA minus 1. Each receive subaddress and transmit subaddress may HI-6120, HI-6121 have a unique circular buffer assignment. The RT decodes the command word count / mode code field to select the unique command descriptor block containing the Control Word, SA pointer, CA pointer and EA pointer ...
Page 60
... Current Address is adjusted to point past last data word accessed. If adjusted Current Address points past End Address, the Current Address is reinitialized to match Start Address and an optional interrupt is generated to notify host that the pre-determined data block was fully transacted. HI-6120, HI-6121 not result in bus transmission. However these messages update the Message Information Word addressed by the ...
Page 61
... Unlike Indexed mode, Data Block completion is based on Buffer Full / Buffer Empty, not number of messages. Buffer size was purposely sized to yield remaining capacity after 2 full-count messages, to illustrate device behavior. The circular buffer should have a 33-word pad beyond its End Address to deal with buffer overrun without data loss. HI-6120, HI-6121 0x0565 (1 + Data Word 32 address) ...
Page 62
... Initialization Factors Based on Message Block Size HI-6120, HI-6121 word in the descriptor block is the Control Word. The second and third words in the descriptor are the Start Address (SA) and Current Address (CA) pointers. The Message Information Buffer Address (MIBA) points to the storage location for the Message Information Word from the next occurring message ...
Page 63
... Descriptor MIB Address tracks number of messages. Full count occurs when N initialized 0-bits become N 1-bits. When full number of messages in block is transacted, an optional interrupt is generated to notify host. HI-6120, HI-6121 The initially-loaded MIB base address value is restricted. Some lower bits of the starting address must be zero so the ...
Page 64
... Buffer Full / Empty interrupt, asserting the INTMES interrupt output. HI-6120, HI-6121 For transmit subaddresses using Circular Buffer Mode 2, the device transmits data from the assigned RAM buffer, starting at the location specified by the CA pointer. The first data word transmitted is stored at the location specified by the CA pointer ...
Page 65
... Data Block completion is based on number of messages, not Buffer Full or Buffer Empty. Example is set to successfully transact four 32 data word receive messages, then generate IXEQZ interrupt for host. The data buffer requires minimal processing by host because message information words are stored separately in MIB. HI-6120, HI-6121 0x057F Data Word 32 ...
Page 66
... This may include undefined mode codes, reserved mode codes, and/or mode codes not implemented in the application. HI-6120, HI-6121 Note: Mode command MC0 “dynamic bus control” cannot be implemented in the device since the HI-6120 cannot act as a Bus Controller. ...
Page 67
... Illegalization Table bit equal to 1, and responds “in form” when the Table bit equals zero. The “in form” response for reserved mode commands 16 through 31 transacts a received or transmitted data word. HI-6120, HI-6121 MODE CODE COMMAND SUMMARY FOR THE HI-6120 / HI-6121 REMOTE TERMINAL MIL-STD-1553B Defined Function Undefined Mode Commands 0 -15 ...
Page 68
... Descriptor Word 1 contains the receive or transmit mode command Control Word. When SMCP is used, just two Control Word bits are used: DBAC (descriptor block accessed) and BCAST (broadcast). HI-6120, HI-6121 When SMCP is enabled, the host need not initialize the mode code command segments in the Descriptor Table. ...
Page 69
... The Interrupt Log Buffer is a 32-word ring buffer located in shared RAM address range 0x0040 to 0x005F. HI-6120, HI-6121 Separate interrupt outputs are provided for hardware interrupts ( INTHW The host programs both pins as either pulsed interrupt ...
Page 70
... After MR pin low to high transition, these steps occur: 1. After 200ns, the states of the following input pins are latched into the Operational Status register: RTA4-RTA0, RTAP, AUTOEN, LOCK and INTSEL. Before READY HI-6120, HI-6121 IIW - Interrupt Identification Word Bit ...
Page 71
... Status Word Bits Register 0x0008 Time-Tag Register 0x0009 Interrupt Log Address Register 0x000A Current Message Information Word Register 0x000B-0x000E Reserved 0x000F Memory Address Pointer (HI-6121 Only) 0x0010 Interrupt Enable Register 0x0011 Time-Tag Utility Register 0x0012 Bus A Select Register 0x0013 Bus B Select Register 0x0014 ...
Page 72
... EEPROM to device RAM address 0x0020. This is part of the Temporary Receive Data Buffer, which does not interfere with terminal initialization. HI-6120, HI-6121 When the device completes auto-initialization, the READY output pin is asserted to the high state initialization error occurred, these events take ...
Page 73
... MC4 or MC20 (decimal). If the Flag status bit was previously inhibited by mode HI-6120, HI-6121 command MC6, inhibit is cleared: The Terminal Flag status bit will be transmitted whenever bit 0 is set in the 1553 Status Word Bits Register. ...
Page 74
... RESET AND INITIALIZATION, Cont. SERIAL EEPROM PROGRAMMING UTILITY The HI-6120 or HI-6121 can program a serial EEPROM via the dedicated EEPROM SPI port for subsequent auto- initialization events. The device copies host-configured registers and RAM (configuration tables and possibly data buffers) to serial EEPROM. ...
Page 75
... RAM operations via the host bus interface, but read and write operations have different signal timing. The HI-6120 parallel host bus interface is capable of faster communication than the HI-6121 Serial Peripheral Interface. Depending on the chosen microprocessor family, the processor’s hardware bus interface an “ ...
Page 76
... FIGURE 21. Generalized Single-Byte Transfer Using SPI Protocol, SCK is Shown for SPI Modes 0 and 3 HI-6120, HI-6121 configuration setting in the HI-6121 to select SPI Mode 0 or Mode 3 because compatibility is automatic. point, the HI-6121 data sheet only shows the SPI Mode 0 SCK signal in timing diagrams. The SPI protocol transfers serial data as 8-bit bytes. Once CE ...
Page 77
... For a register read or write negated after the 2-byte data word is transferred. RAM AND REGISTER INDIRECT ADDRESSING Refer to the HI-6121 SPI command set shown in Table 2. SPI commands other than fast-access use an address pointer to indicate the address for read or write transactions. ...
Page 78
... Several other HI-6121 SPI commands load or otherwise modify the primary address pointer before initiating a read or write process. These commands were tailored to the specific needs of HI-6121 Remote Terminal host software. Using a single-byte SPI command, the address pointer can be directly loaded with the memory address for the descriptor table Control Word corresponding to the last completed MIL-STD-1553 command ...
Page 79
... HOST SERIAL PERIPHERAL INTERFACE, Cont. (HI-6121 ONLY) Command Read Operation 0x68 Read the location addressed by the memory address pointer. Write the value just read into the memory address pointer. Then read. 0x70 Add 1 to the memory address pointer. Read value at newly addressed location and write it into the memory address pointer ...
Page 80
... Write storage address of last-written Interrupt Address Word to the address pointer in register 15, then read the Interrupt Address Word from the Interrupt Log buffer. Decrement memory address pointer after read operation. TABLE 2. SUMMARY OF HI-6121 SERIAL PERIPHERAL INTERFACE (SPI) COMMANDS HI-6120, HI-6121 FAST-ACCESS COMMAND BITS ...
Page 81
... OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response). **Terminal is using “illegal command detection” and command is illegal HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word No change No change No change message is ignored ...
Page 82
... Also includes transmitting RT response with Message Error or Busy status followed by no data words. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit set. BCAST bit updated. DPB bit toggles. DBAC bit set. ...
Page 83
... Terminal is using “illegal command detection” and command is legal OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response). HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit set. ...
Page 84
... OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response). **Terminal is using “illegal command detection” and command is illegal. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit set. ...
Page 85
... Descriptor Table control word.) FOLLOWING PAGES LIST THE DETAILED RESPONSES FOR MODE CODE COMMANDS HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit set. BCAST bit updated. ...
Page 86
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit set ...
Page 87
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit set ...
Page 88
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit set ...
Page 89
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 90
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 91
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 92
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 93
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 94
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 95
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit set ...
Page 96
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 97
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 98
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 99
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 100
... The Illegalization Table set the BCR status bit and bit equals 0 * suppress status response. MC20 continues on next page HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit reset. BCAST bit reset. DPB bit toggles. ...
Page 101
... TXINHA or TXINHB for the inactive bus to reenable transmit if the host used this pin to shut down transmit only for an earlier MC4 or MC20 command. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit set ...
Page 102
... Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word No change ...
Page 103
... BCR status bits. * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” HI-6120, HI-6121 SUMMARY OF MESSAGE RESPONSES FOR THE HI-6120 / HI-6121 REMOTE TERMINAL Bits Updated in Descriptor Control Word DBAC bit set. ...
Page 104
... Point “A ” in Figure 25 unless otherwise specified) Output Voltage Direct coupled Transformer coupled Output Noise Output Dynamic Offset Voltage Direct coupled Transformer coupled Output Resistance Output Capacitance HI-6120, HI-6121 -0 +5 Vp-p +1.0 A 1.0 W 275°C for 10 sec. 175°C -65°C to +150°C SYMBOL ...
Page 105
... AC ELECTRICAL CHARACTERISTICS VDD = 3.3 V, GND = 0V Operating Temperature Range (unless otherwise specified). A PARAMETER HI-6121 INTERFACE TIMING (SPI Host Bus Interface) CE set-up time to first SCK rising edge CE hold time after last SCK falling edge CE SPI SI Data set-up time to SCK rising edge SPI SI Data hold time after SCK rising edge ...
Page 106
... HOST WRITE IN WORD MODE (16-BIT BUS WIDTH) using BTYPE = 1 (”Intel Style” - showing a one-word write cycle. Successive writes to sequential addresses have same timing. A15 WAIT D15:0 FIGURE 21. Register and RAM Write Operations for BTYPE = 1 HI-6120, HI-6121 SYMBOL Clock period t CYC Write cycle t Read/Write inactive time t INACT ...
Page 107
... BTYPE = 0 (”Motorola Style” - Single Read/Write Strobe showing a one-word write cycle. Successive writes to sequential addresses have same timing. A15 STR WAIT D15:0 FIGURE 22. Register and RAM Write Operations for BTYPE = 0 HI-6120, HI-6121 Read/Write Strobe showing 2 bytes written for a single 16-bit word ADDRESS INACT ...
Page 108
... This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted. FIGURE 23. Register and RAM Read Operations for BTYPE = 1 HI-6120, HI-6121 OE Output Enable and ...
Page 109
... This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted. FIGURE 24. Register and RAM Read Operations for BTYPE = 0 HI-6120, HI-6121 Read/Write Strobe showing two bytes read for a single 16-bit word ...
Page 110
... Manchester Encoder TXINHA/B Point “A “ D TRANSMITTER Tx Data from Manchester Encoder TXINHA/B 52.5 (.75 Zo (.5 Zo) 52.5 (.75 Zo) Figure 26. Transformer Coupled Test Circuits HI-6120, HI-6121 1:2.5 BUSA/B BUSA/B Isolation Transformer 2.5 Isolation Transformer Figure 25. Direct Coupled Test Circuits Point “A ” T 1:2.5 BUSA/B ...
Page 111
... PACKAGE STYLE 100 pin PQFP HI-6120PQI / T 52 pin PQFP HI-6121PQI / T PIN CONFIGURATION FOR HI-6121, 64-PIN QFN PACKAGE Notes 1 . All VCC, VCCP and GND pins must be connected. 2. See data sheet page 1 for HI-6121, 52-Pin PQFP Package Configuration. HI-6120, HI-6121 q CONDITION JA Mounted on 60.9 circuit board ° ...
Page 112
... PIN CONFIGURATION FOR HI-6120, 100-PIN PQFP PACKAGE Notes 1 . All VCC, VCCP and GND pins must be connected. 2. See data sheet page 1 for HI-6121, 52-Pin PQFP Package Configuration. VCC - 1 GND - 2 D12 - 3 D13 - 4 D14 - 5 D15 - 6 COMP - MODE - 9 STR - 10 VCC - 11 BTYPE - 12 MCLK - 13 GND - 14 WAIT - 15 ...
Page 113
... ORDERING INFORMATION HI-6120PQ x x PART NUMBER Blank F PART NUMBER PART NUMBER PQ HI-6121PQ x x PART NUMBER Blank F PART NUMBER PART NUMBER PC PQ HI-6120, HI-6121 PACKAGE DESCRIPTION Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free RoHS compliant) TEMPERATURE RANGE FLOW -40°C TO +85°C I -55° ...
Page 114
... Standard 95) 64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) .354 BSC (9.00) .354 Top View BSC (9.00) .039 max (1.00) HI-6120 & HI-6121 PACKAGE DIMENSIONS .394 BSC SQ (10.0) .063 typ (1.6) .079 .008 ± (2.00 ± .20) Heat sink pad on bottom of package. Heat sink must be left floating or connected to VDD. ...
Page 115
... BSC SQ (16.0) .039 typ (1.0) .059 .004 ± (1.50 ± .10) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-6120 & HI-6121 PACKAGE DIMENSIONS .551 BSC SQ (14.0) (0.20) See Detail A .055 .002 ± (1.40 ± .05) HOLT INTEGRATED CIRCUITS 115 inches (millimeters) Package Type: 100PQS ...