mk60dn512zvll10 Freescale Semiconductor, Inc, mk60dn512zvll10 Datasheet - Page 64

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mk60dn512zvll10

Manufacturer Part Number
mk60dn512zvll10
Description
Up To 100 Mhz Arm Cortex-m4 Core With Dsp
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Peripheral operating requirements and behaviors
6.8.10 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
64
Num
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
Symbol
t
t
f
t
t
t
t
fpp
fpp
fpp
TLH
THL
t
OD
WL
WH
OD
ISU
IH
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
Operating voltage
Clock frequency (low speed)
Clock frequency (SD\SDIO full speed)
Clock frequency (MMC full speed)
Clock frequency (identification mode)
Clock low time
Clock high time
Clock rise time
Clock fall time
SDHC output delay (output valid)
SDHC input setup time
SDHC input hold time
Description
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Table 46. SDHC switching specifications
SD3
SD6
Figure 28. SDHC timing
SD2
SD7
Preliminary
Card input clock
SD8
SD1
Min.
2.7
-5
0
0
0
0
7
7
5
0
Freescale Semiconductor, Inc.
Max.
400
400
3.6
6.5
25
20
3
3
MHz
MHz
Unit
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
V

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