cym1840 Cypress Semiconductor Corporation., cym1840 Datasheet - Page 3

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cym1840

Manufacturer Part Number
cym1840
Description
256k X 32 Static Ram Module
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Switching Characteristics
READ CYCLE
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Notes:
RC
AA
OHA
ACS
LZCS
HZCS
PU
PD
WC
SCS
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
3.
4.
5.
6.
Parameter
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
At any given temperature and voltage condition, t
t
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
OL
HZCS
/I
OH
and t
and 30-pF load capacitance.
HZWE
[6]
Read Cycle Time
Address to Data Valid
Output Hold from Address Change
CS LOW to Data Valid
CS LOW to Low Z
CS HIGH to High Z
CS LOW to Power-Up
CS HIGH to Power-Down
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
are specified with C
L
Over the Operating Range
Description
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage.
[4]
[4, 5]
[5]
HZCS
is less than t
LZCS
[3]
for any given device.
3
Min.
20
20
18
18
15
13
5
5
0
2
2
2
0
0
1840-20
Max.
20
20
20
20
15
Min.
25
25
20
20
20
15
5
5
0
2
2
2
0
0
1840-25
Max.
25
25
20
25
15
Min.
30
30
25
25
25
15
5
5
0
2
2
2
0
0
1840-30
Max.
CYM1840
30
30
20
30
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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