ucn5895 Allegro MicroSystems, Inc., ucn5895 Datasheet - Page 4

• Manufacturer Part Number: ucn5895
• Description: Bimos Ii 8-bit Serial Input, Latched Source Drivers
• Manufacturer: Allegro MicroSystems, Inc.

5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
A.
B.
C.
D.
E.
F.
G.
on the logic “0” to logic “1” transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE tied
high) will require that the OUTPUT ENABLE input be high during serial
data entry.
are disabled (OFF) without affecting the information stored in the
latches or shift register. With the OUTPUT ENABLE input low, the
outputs are controlled by the state of their respective latches.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
BLANKING
Serial Data present at the input is transferred to the shift register
Information present at any register is transferred to its respective
When the OUTPUT ENABLE input is high, all of the output buffers
STROBE
DATA IN
CLOCK
Minimum Data Active Time Before Clock Pulse
Minimum Data Active Time After Clock Pulse
Minimum Data Pulse Width ........................................................ 150 ns
Minimum Clock Pulse Width ...................................................... 150 ns
Minimum Time Between Clock Activation and Strobe ............... 300 ns
Minimum Strobe Pulse Width ..................................................... 100 ns
Typical Time Between Strobe Activation and
OUT
(Data Set-Up Time) ................................................................. 75 ns
(Data Hold Time) ..................................................................... 75 ns
Output Transition .................................................................... 1.0 s
(V
N
DD
= 5.0 V, Logic Levels are V
A
C
B
D
E
F
G
DD
and Ground)
Dwg. No. A-12,649A