adsst-em-3035k Analog Devices, Inc., adsst-em-3035k Datasheet - Page 2

• Manufacturer Part Number: adsst-em-3035k
• Description: Salem Three-phase Electronic Energy Meter
• Manufacturer: Analog Devices, Inc.

ADSST-EM-3035
ADSST-2185KST-133 (DSP) SPECIFICATION
FEATURES
30 ns Instruction Cycle 33 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Three-Bus Architecture Allows Dual Operand Fetches
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby Power
Low Power Dissipation in Idle Mode
ADSP-2100 Family Code Compatible, with Instruction
40 kBytes of On-Chip RAM, Configured as
Dual Purpose Program Memory for Both Instruction
Independent ALU, Multiplier/Accumulator, and Barrel
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Programmable 16-Bit Interval Timer with Prescaler
100-Lead TQFP
16-Bit Internal DMA Port for High Speed Access to On-
4 MBytes Byte Memory Interface for Storage of Data
8-Bit DMA to Byte Memory for Transparent Program and
I/O Memory Interface with 2048 Locations Supports
Programmable Memory Strobe and Separate I/O
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Automatic Booting of On-Chip Program Memory from
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port Emulator Interface Supports Debugging in Final Systems
in Every Instruction Cycle
Dissipation with 100 Cycle Recovery from Power-Down
Condition
Set Extensions
8 KWords On-Chip Program Memory RAM and
8 KWords On-Chip Data Memory RAM
and Data Storage
Shifter Computational Units
Looping Conditional Instruction Execution
Chip Memory (Mode Selectable)
Tables and Program Overlays
Data Memory Transfers (Mode Selectable)
Parallel Peripherals (Mode Selectable)
Memory Space Permits Glueless System Design
(Mode Selectable)
Hardware and Automatic Data Buffering
Byte-Wide External Memory, e.g., EPROM, or through
Internal DMA Port
–2–
GENERAL DESCRIPTION
The ADSST-2185KST-133 is a single-chip microcomputer
optimized for digital signal processing (DSP) and other high
speed numeric processing applications.
The ADSST-2185KST-133 combines the ADSP-2100 family
base architecture (three computational units, data address
generators, and a program sequencer) with two serial ports, a
16-bit internal DMA port, a byte DMA port, a programmable
timer, Flag I/O, extensive interrupt capabilities, and on-chip
program and data memory.
The ADSST-2185KST-133 integrates 40 kBytes of on-chip
memory configured as 8 Kwords (24-bit) of program RAM and
8 Kwords (16-bit) of data RAM. Power-down circuitry is also
provided to meet the low power needs of battery operated portable
equipment. The ADSST-2185KST-133 is available in a 100-lead
TQFP package.
In addition, the ADSST-2185KST-133 supports instructions
that include bit manipulations, bit set, bit clear, bit toggle, bit
test new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers, and global interrupt masking for increased flexibility.
Fabricated in a high speed, double metal, low power, CMOS
process, the ADSST-2185KST-133 operates with a 25 ns
instruction cycle time. Every instruction can execute in a single
processor cycle.
The ADSST-2185KST-133’s flexible architecture and com-
prehensive instruction set allow the processor to perform
multiple operations in parallel. In one processor cycle, the
ADSST-2185KST-133 can:
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•
•
•
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DATA ADDRESS
GENERATORS
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
This takes place while the processor continues to:
DAG 1
ALU
ARITHMETIC UNITS
Receive and transmit data through the two serial ports
Receive and/or transmit data through the internal DMA port
Receive and/or transmit data through the byte DMA port
Decrement timer
ADSP-2100 BASE
ARCHITECTURE
DAG 2
MAC
SHIFTER
SEQUENCER
Figure 1. Functional Block Diagram
PROGRAM
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
PROGRAM
16K
MEMORY
SPORT 0
SERIAL PORTS
POWER-DOWN
24
CONTROL
MEMORY
SPORT 1
16K
MEMORY
DATA
16
PROGRAMMABLE
TIMER
FLAGS
AND
I/O
FULL MEMORY
CONTROLLER
EXTERNAL
EXTERNAL
EXTERNAL
INTERNAL
ADDRESS
HOST MODE
BYTE DMA
PORT
DATA
DATA
BUS
BUS
BUS
DMA
MODE
OR
REV. 0