saa5249 NXP Semiconductors, saa5249 Datasheet - Page 25

• Manufacturer Part Number: saa5249
• Description: Integrated Vip And Teletext With Background Memory Controller Ivt1.1bmcx
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Notes
1. The dash ( ) indicates these bits are inactive and must be written to logic 0 for future compatibility.
2. All bits in registers R0 to R10 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6
3. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white
4. TB must be set to logic 0 for normal operation.
5. The I
Table 8
1996 Nov 07
R0 ADVANCED CONTROL - auto increments to register 1
R11/R11B SELECT
DISABLE ODD/EVEN
DISPLAY STATUS ROW
DISABLE HDR ROLL
AUTO ODD/EVEN
FREE RUN PLL
X24 POS
R1 MODE - auto increments to register 2
T0, T1
TCS ON
DEW/FULL FIELD
DISABLE PKT 26
ACQ ON/OFF
7 + P/8-BIT
VCS TO SCS
R2 PAGE REQUEST ADDRESS - auto increments to register 3
COL SCO - SC2
TB
R3 PAGE REQUEST DATA - does not auto increment (see Table 9)
CLEAR B.M.
R5 NORMAL DISPLAY CONTROL - auto increments to register 6
R6 NEWSFLASH/SUBTITLE DISPLAY CONTROL - auto increments to register 7; (note 1)
PON
TEXT
COR
BKGND
Integrated VIP and Teletext with
Background Memory Controller
which are set to logic 1.
(00000111) as the acquisition circuit is enabled but the page is on hold.
2
C-bus slave address is 0010001.
Register description
selects reading of R11 or R11B
forces ODD/EVEN output LOW when logic 1
when SET = 1 and R1D6 = 1 open (8-bit mode) then all the text display is blanked
out apart from the status row, this allows the page memory to be used for
non-textural data, such as in the German TOP system
disables green rolling header and time
when set forces ODD/EVEN LOW if any TV picture displayed, if DISABLE
ODD/EVEN = 0
will force the PLL to free run in all conditions
automatic display of FASTEXT prompt row when logic 1
interlace/non-interlace 312/313 line control (see Table 10)
text composite sync or direct sync select (see Table 10 for FFB mode selection)
field-flyback or full-channel mode
disable automatic processing of packet 26
acquisition circuits turned off when logic 1
7-bits with parity checking or 8-bit mode
when logic 1 enables display of messages with 60 Hz input signal
point to start column for page request data (see Table 9)
must be logic 0 for normal operation
when set to logic 1. Useful when transmission channel changes
picture on
text on
contrast reduction on
background colour on
25
Preliminary specification
SAA5249