m368l3223ctl Samsung Semiconductor, Inc., m368l3223ctl Datasheet

no-image

m368l3223ctl

Manufacturer Part Number
m368l3223ctl
Description
256mb Ddr Sdram Module Unbuffered 184pin Dimm 64-bit Non-ecc/parity
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
M368L3223CTL
184pin Unbuffered DDR SDRAM MODULE
256MB DDR SDRAM MODULE
(32Mx64 based on 32Mx8 DDR SDRAM)
Unbuffered 184pin DIMM
64-bit Non-ECC/Parity
Revision 0.3
May. 2002
Rev. 0.3 May. 2002

Related parts for m368l3223ctl

m368l3223ctl Summary of contents

Page 1

... M368L3223CTL 256MB DDR SDRAM MODULE (32Mx64 based on 32Mx8 DDR SDRAM) Unbuffered 184pin DIMM 64-bit Non-ECC/Parity 184pin Unbuffered DDR SDRAM MODULE Revision 0.3 May. 2002 Rev. 0.3 May. 2002 ...

Page 2

... M368L3223CTL Revision History Revision 0 (Oct 2001) 1. First release for internal usage Version 0.1(November,2001) - Revised "Absolute maximum rating" table in page 38. . Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V . Changed "power dissipation" value from 8W to 12W. - Revised AC parameter table DDR266A DDR266B Min. Max. ...

Page 3

... M368L3223CTL DDR SDRAM 184pin DIMM 32Mx64 DDR SDRAM 184pin DIMM based on 32Mx8 GENERAL DESCRIPTION The Samsung M368L3223CTL is 32M bit x 64 Double Data Rate SDRAM high density memory modules. The Samsung M368L3223CTL consists of eight CMOS 32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages mounted on a 184pin glass-epoxy substrate ...

Page 4

... M368L3223CTL Functional Block Diagram CS0 DQS0 DM0 DQ0 I/O 7 DQ1 I DQ2 I/O 1 DQ3 I/O 0 DQ4 I/O 5 I/O 4 DQ5 I/O 3 DQ6 I/O 2 DQ7 DQS1 DM1 DQ8 I/O 7 DQ9 I DQ10 I/O 1 DQ11 I/O 0 I/O 5 DQ12 I/O 4 DQ13 I/O 3 DQ14 DQ15 I/O 2 DQS2 DM2 DM CS DQ16 I/O 7 DQ17 I DQ18 I/O 1 DQ19 I/O 0 DQ20 ...

Page 5

... M368L3223CTL ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Voltage on V supply relative to Vss DDQ Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...

Page 6

... M368L3223CTL DDR SDRAM IDD spec table Symbol B3(DDR333@CL=2.5) IDD0 920 IDD1 1120 IDD2P 24 IDD2F 240 IDD2Q 160 IDD3P 320 IDD3N 480 IDD4R 1480 IDD4W 1400 IDD5 1560 Normal 24 IDD6 Low power 12 IDD7A 2800 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. ...

Page 7

... M368L3223CTL Output Input/Output CAPACITANCE Parameter Input capacitance Input capacitance(CKE ) 0 Input capacitance Input capacitance( CLK , CLK CLK Data & DQS input/output capacitance(DQ Input capacitance(DM ~ 184pin Unbuffered DDR SDRAM MODULE V =0.5*V tt DDQ R =50 T Z0=50 V =0.5*V C =30pF LOAD Output Load Circuit (SSTL_2 ...

Page 8

... M368L3223CTL AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2.0 Clock cycle time CL=2 ...

Page 9

... M368L3223CTL Parameter Symbol Mode register set cycle time tMRD DQ & DM setup time to DQS tDS DQ & DM hold time to DQS tDH Control & Address input pulse width tIPW DQ & DM input pulse width tDIPW Power down exit time tPDEX Exit self refresh to non-Read command ...

Page 10

... M368L3223CTL 8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) 280 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) 0 0.25 0.5 This derating table is used to increase t is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V ...

Page 11

... M368L3223CTL Command Truth Table COMMAND Register Extended MRS Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address ...

Page 12

... M368L3223CTL PACKAGE DIMENSIONS 1.25 (31.75 0.250 (6.350) 0.26 (6.62) 2.175 Detail A Tolerances : ± 0.005(.13) unless otherwise specified. The used device is 32Mx8 DDR SDRAM, TSOP. SDRAM Part NO : K4H560838C. 184pin Unbuffered DDR SDRAM MODULE 5.25 ± 0.005 (133.350 ± 0.13) 5.077 (128.950) A 2.55 1.95 (64.77) (49.53) 0.157 (4.00) 0.1496 (3.80) 0.071 (1.80 ) (1.270) Detail B Units : Inches (Millimeters) ...

Related keywords