mt5lsdt872ay-13e Micron Semiconductor Products, mt5lsdt872ay-13e Datasheet

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mt5lsdt872ay-13e

Manufacturer Part Number
mt5lsdt872ay-13e
Description
32mb, 64mb, 128mb X72, Sr 168-pin Sdram Udimm
Manufacturer
Micron Semiconductor Products
Datasheet
SYNCHRONOUS
DRAM MODULE
Features
• 168-pin, dual in-line memory module (DIMM)
• PC100- and PC133-compliant
• Unbuffered
• 32MB (4 Meg x 72), 64MB (8 Meg x 72), 128MB (16
• Supports ECC error detection and correction
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can
• Internal SDRAM banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, including CONCURRENT AUTO
• Self Refresh Mode: 64ms, 4,096-cycle refresh for
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
• Gold edge contacts
Table 1:
CL = CAS (READ) latency
Table 2:
32, 64, 128MB x 64 SDRAM DIMM
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
MODULE
MARKING
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
Meg x 72)
edge of system clock
be changed every clock cycle
PRECHARGE, and Auto Refresh Modes
32MB and 64MB; 64ms, 8,192-cycle refresh for
128MB
-13E
-133
-10E
FREQUENCY
133 MHz
133 MHz
100 MHz
CLOCK
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
Timing Parameters
Address Table
CL = 2
ACCESS TIME
5.4ns
9ns
CL = 3
5.4ns
7.5ns
SETUP
64Mb (4 Meg x 16)
TIME
2ns
1.5
1.5
4K (A0-A11)
256 (A0-A7)
4 (BA0, BA1)
1 (S0#, S2#)
32MB
4K
HOLD
TIME
1ns
0.8
0.8
1
NOTE:
MT5LSDT472A – 32MB
MT5LSDT872A(I) – 64MB
MT5LSDT1672A(I) – 128MB
For the latest data sheet, please refer to the Micron
site:
Options
• Package
• Operating Temperature Range
• Frequency / CAS Latency
Standard 1.00in. (25.40mm)
168-pin DIMM (standard)
168-pin DIMM (lead-free)
Commercial (0°C to +65°C)
Industrial (-40°C to +85°C)
7.5ns (133 MHz) / CL = 2
7.5ns (133 MHz) / CL = 3
8ns (100 MHz) / CL = 2
Figure 1: 168-Pin DIMM (MO-161)
32MB, 64MB, 128MB (x72, SR)
www.micron.com/products/modules
128Mb (8 Meg x 16)
1. Consult Micron for product availability.
2. Industrial Temperature option available in -133
4K (A0-A11)
512 (A0-A8)
4 (BA0, BA1)
1 (S0#, S2#)
speed only.
64MB
4K
168-PIN SDRAM UDIMM
©2004 Micron Technology, Inc. All rights reserved.
256Mb (16 Meg x 16)
8K (A0-A12)
512 (A0-A8)
4 (BA0, BA1)
1 (S0#, S2#)
128MB
8K
Marking
None
-13E
-10E
-133
Y
G
I
2
1
®
Web

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mt5lsdt872ay-13e Summary of contents

Page 1

... SYNCHRONOUS DRAM MODULE Features • 168-pin, dual in-line memory module (DIMM) • PC100- and PC133-compliant • Unbuffered • 32MB (4 Meg x 72), 64MB (8 Meg x 72), 128MB (16 Meg x 72) • Supports ECC error detection and correction • Single +3.3V power supply • Fully synchronous; all signals registered on positive edge of system clock • ...

Page 2

... Table 3: Part Numbers PART NUMBER MT5LSDT472AG-13E_ MT5LSDT472AY-13E_ MT5LSDT472AG-133_ MT5LSDT472AY-133_ MT5LSDT472AG-10E_ MT5LSDT472AY-10E_ MT5LSDT872AG-13E_ MT5LSDT872AY-13E_ MT5LSDT872A(I)G-133_ MT5LSDT872A(I)Y-133_ MT5LSDT872AG-10E_ MT5LSDT872AY-10E_ MT5LSDT1672AG-13E_ MT5LSDT1672AY-13E_ MT5LSDT1672A(I)G-133_ MT5LSDT1672A(I)Y-133_ MT5LSDT1672AG-10E_ MT5LSDT1672AY-10E_ NOTE: The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes ...

Page 3

... CB0 42 CKO 63 NOTE: 1. Pin 126 is NC for 32MB and 64MB modules, or A12 for the 128MB module. Figure 2: Pin Locations (168-Pin DIMM) Front View U1 PIN 1 Back View PIN 168 32, 64, 128MB x 64 SDRAM DIMM SD5C4_8_16x72AG.fm - Rev. C 6/04 EN 32MB, 64MB, 128MB (x72, SR) ...

Page 4

... MODE REGISTER SET command. Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Input/Output Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module ...

Page 5

... Input/Output ECC check bits. Supply Power Supply: +3.3V ±0.3V. DD Supply Ground. SS – Do Not Use: These pins are not used on these modules, but are assigned pins on other modules in this product family. – Not Connected: These pins are not connected on these modules. 5 168-PIN SDRAM UDIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...

Page 6

... A0-A11(32MB/64MB) A0-A12(128MB) BA0-1 Note: 1. All resistor values are 10 unless otherwise specified. 2. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at www.micron.com/numberguide. 32, 64, 128MB x 64 SDRAM DIMM SD5C4_8_16x72AG.fm - Rev. C 6/04 EN 32MB, 64MB, 128MB (x72, SR) ...

Page 7

... EEPROM device (DIMM) occur via a standard IIC bus using the DIMM’s SCL (clock) and SDA (data) signals. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Initialization SDRAMs must be powered up and initialized in a predefined manner ...

Page 8

... M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. For the 128MB module, Address A12 (M12) is undefined but should be driven LOW during loading of the mode register. ...

Page 9

... For a burst length of one, A0–Ai select the unique col- umn to be accessed, and mode register bit M3 is ignored for 32MB module for 64MB and 128MB modules 32, 64, 128MB x 64 SDRAM DIMM SD5C4_8_16x72AG.fm - Rev. C 6/04 EN 32MB, 64MB, 128MB (x72, SR) ...

Page 10

Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ ...

Page 11

... Write Inhibit/Output High-Z NOTE: 1. A0–A11 define the op-code written to the mode register, and for the 128MB module, A12 should be driven LOW. 2. A0–A11 (32MB and 64MB) or A0–A12 (128MB) provide device row address, and BA0, BA1 determine which device bank is made active. 3. A0– ...

Page 12

Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...

Page 13

Table 12: I Specifications and Conditions – 64MB DD Notes 11, 13; notes appear following the parameter tables; V PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst = 2; READ WRITE (MIN) STANDBY ...

Page 14

Table 15: Electrical Characteristics and Recommended AC Operating Conditions Notes 11, 31; notes appear following the parameter tables CHARACTERISTICS PARAMETER Access time from CLK (pos. edge Address hold ...

Page 15

Table 16: AC Functional Characteristics Notes 11, 31; notes appear following the parameter tables PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup ...

Page 16

... Refer to device data sheet for timing waveforms. 32. The value of ules is calculated from 33. Leakage number reflects the worst-case leakage t CKS; clock(s) speci- possible through the module pin, not what each memory device contributes plus RP; clock(s) 16 168-PIN SDRAM UDIMM t WR ...

Page 17

SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions, as indicated in Figure 6, Data Validity, and Figure ...

Page 18

Table 17: EEPROM Device Select Code The most significant bit (b7) is sent first Memory Area Select Code (two arrays) Protection Register Select Code Table 18: EEPROM Operating Modes MODE RW BIT Current Address Read 1 Random Address Read 0 ...

Page 19

Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...

Page 20

... Total Number of Spd Memory Bytes 2 Memory Type 3 Number of Row Addresses 4 Number of Column Addresses 5 Number of Banks 6 Module Data Width 7 Module Data Width (Continued) 8 Module Voltage Interface Levels 9 t SDRAM Cycle Time, CK (CAS Latency = 3) 10 SDRAM Access from Clock, (CAS Latency = 3) 11 Module Configuration Type ...

Page 21

... RC 42-61 Reserved 62 SPD Revision 63 Checksum for Bytes 0-62 64 Manufacturer’s JEDEC ID Code 65-71 Manufacturer’s JEDEC ID Code (Continued) 72 Manufacturing Location 73-90 Module Part Number (ASCII) 91 PCB Identification Code 92 Identification Code (Continued) 93 Year of Manufacture in BCD 94 Week of Manufacture in BCD 95-98 Module Serial Number 99-125 Manufacturer-Specific Data (RSVD) 126 ...

Page 22

R (2X) U1 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 2.625 (66.68) PIN 1 (PIN 85 ON BACKSIDE) NOTE: All dimensions in inches (millimeters) Data Sheet Designation Released (No Mark): This data sheet ...

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