mt16d832m-6-x Micron Semiconductor Products, mt16d832m-6-x Datasheet - Page 9

• Manufacturer Part Number: mt16d832m-6-x
• Description: Not Recommended For New Designs
• Manufacturer: Micron Semiconductor Products

NOT RECOMMENDED FOR NEW DESIGNS
NOTES
1. All voltages referenced to V
2. This parameter is sampled. Capacitance is
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. V
9. In addition to meeting the transition rate
10.If CAS# = V
11.If CAS# = V
12.Measured with a load equivalent to two TTL gates
13.If CAS# is LOW at the falling edge of RAS#, Q will
4, 8 Meg x 32 DRAM SIMMs
DM44_2.p65 – Rev. 9/98
measured using MIL-STD-883C, Method 3012.1
(1 MHz AC, V
RMS).
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
indicate cycle time at which proper operation over
the full temperature range is ensured.
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the
refresh requirement is exceeded.
= 2.5ns for EDO.
measuring timing of input signals. Transition
times are measured between V
between V
specification, all input signals must transit
between V
monotonic manner.
the last valid READ cycle.
and 100pF, V
be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS#
must be pulsed HIGH for
CC
IH
is dependent on output loading and cycle
(MIN) and V
IH
IL
IH
IL
and V
and V
, data output may contain data from
OL
, data output is High-Z.
DD
= 0.8V and V
= 4.5V, DC bias = 2.4V at 15mV
IL
(MAX) are reference levels for
IH
IL
).
(or between V
t
t
CP.
T = 5ns for FPM and
SS
OH
.
= 2V.
IH
and V
IL
and V
IL
(or
IH
) in a
t
REF
t
T
9
14.The
15.The
16.Either
17.
18.These parameters are referenced to CAS# leading
19.OE# is tied permanently LOW; LATE WRITE or
20.A HIDDEN REFRESH may also be performed after
21.The 3ns minimum is a parameter guaranteed by
22.Column address changed once each cycle.
23.16MB module values will be half of those shown.
24.For the FPM option,
25.Applies to both EDO and FPM modules.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
by
without the
always be met.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
by
without the
must always be met.
cycle.
t
achieves the open circuit condition and is not
referenced to V
edge in EARLY WRITE cycles.
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
a WRITE cycle. In this case, WE# = LOW and OE# =
HIGH.
design.
RAS# or CAS# signal to transition HIGH. In
comparison,
by the latter of the RAS# and CAS# signals to
transition HIGH.
RCD was greater than the specified
RAD was greater than the specified
OFF (MAX) defines the time at which the output
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
AA (
CAC (
t
t
RCD (MAX) limit is no longer specified.
RAD (MAX) limit is no longer specified.
t
RCH or
t
RAC and
t
RAC [MIN] no longer applied). With or
t
t
RAD (MAX) limit,
RCD (MAX) limit,
t
OFF on an EDO option is determined
OH
t
RRH must be satisfied for a READ
t
or V
CAC no longer applied). With or
t
OFF is determined by the first
OL
.
4, 8 MEG x 32
DRAM SIMMs
t
t
AA,
AA and
©1998, Micron Technology, Inc.
t
RAC and
t
t
RAD (MAX)
RCD (MAX)
t
CAC must
t
t
RAD
t
RCD
CAC