mt16jsf25664hy-1g1 Micron Semiconductor Products, mt16jsf25664hy-1g1 Datasheet - Page 4

• Manufacturer Part Number: mt16jsf25664hy-1g1
• Description: 2gb X64, Dr 204-pin Ddr3 Sdram Sodimm
• Manufacturer: Micron Semiconductor Products

Table 5:
PDF: 09005aef83021ee3/Source: 09005aef83021f5a
JSF16C256x64H.fm - Rev. A 3/08 EN
ODT0, ODT1
RAS#, CAS#,
CKE0, CKE1
CK0, CK0#,
CK1, CK1#
DQS#[7:0]
DQS[7:0],
DQ[63:0]
Symbol
DM[7:0]
S0#, S1#
EVENT#
A[13:0]
BA[2:0]
RESET#
V
SA[2:0]
V
WE#
REF
SDA
DDSPD
V
SCL
DD
CA
Pin Descriptions
(open drain)
(LVCMOS)
Output
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands. The address inputs also provide the op-code during the mode
register command set
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM.
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of the DQS. Although the DM pins are input-only, the DM loading is designed
to match that of the DQ and DQS pins.
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be
ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: RESET# is an active LOW CMOS input referenced to V
a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
× V
likely be unterminated, heavily loaded, and have very slow slew rates. A slow slew rate
receiver design is recommended along with implementing on-chip noise filtering to
prevent false triggering (RESET# assertion minimum pulse width is 100ns).
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: These pins are used to configure the temperature sensor/SPD
EEPROM address range on the I
Serial clock for temperature sensor/SPD EEPROM: SCL is used to synchronize the
communication to and from the temperature sensor/SPD EEPROM.
Data input/output: Bidirectional data bus.
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of
the temperature sensor/SPD EEPROM on the module on the I
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
temperature thresholds have been exceeded.
Power supply: 1.5V ±0.075V. The component V
module V
Temperature sensor/SPD EEPROM power supply: +3.0V to +3.6V.
Reference voltage: Control, command, and address (V
DD
Q. RESET# assertion and deassertion are asynchronous. System applications will most
DD
.
.
A[13:0] address the 1Gb DDR3 devices.
2GB (x64, DR) 204-Pin DDR3 SDRAM SODIMM
4
2
C bus.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
DD
and V
DD
DD
/2).
SS
Q are connected to the
2
.The RESET# input receiver is
C bus.
©2008 Micron Technology, Inc. All rights reserved
DD
Q and DC LOW ≤ 0.2