mt8lsdt3264ay-13e Micron Semiconductor Products, mt8lsdt3264ay-13e Datasheet - Page 20

• Manufacturer Part Number: mt8lsdt3264ay-13e
• Description: 256mb X64, Sr , 512mb X64, Dr 168-pin Sdram Udimm
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef807b3771/Source: 09005aef807b37b5
SD8_16C32_64x64AG.fm - Rev. D 3/05 EN
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
24. Auto precharge mode only. The precharge timing budget (
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. For -10E, CL= 2 and
30. CKE is HIGH during refresh command period
31. The value of
32. Refer to device data sheet for timing waveforms.
33. Leakage number reflects the worst-case leakage possible through the module pin, not
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including
used to reduce the data rate.
7.5ns for -133 and 7ns for -10E after the first clock delay, after the last WRITE is exe-
cuted. May not exceed limit set for precharge mode.
t
t
limit is actually a nominal value and does not result in a fail value.
45ns.
what each memory device contributes.
AC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design.
CK = 7.5ns.
256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM
t
RAS used in -13E speed grade module SPDs is calculated from
t
CK = 10ns; for -133, CL = 3 and
20
t
WR, and PRECHARGE commands). CKE may be
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RFC (MIN) else CKE is LOW. The I
t
CK = 7.5ns; for -13E, CL = 2 and
©2003 Micron Technology, Inc. All rights reserved.
t
RP) begins 7ns for -13E;
t
RC -
Notes
t
RP =
DD
6