saa4700 NXP Semiconductors, saa4700 Datasheet - Page 4

• Manufacturer Part Number: saa4700
• Description: Vps Dataline Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
PINNING
External reset
The circuit provides an internal
power-on reset. When using this
facility pin 10 should be connected to
V
(RESET = LOW) is to be used pin 10
should be prepared by connecting pin
10 via a 10 k pull-up resistor to V
Reset forces the following:
- I
- DAV output to go HIGH (pin 12)
- I
CVBS input
The CVBS signal is applied to the
sync separator (pin 2) via a
decoupling capacitor and to the data
slicer (pin 1) via an RC high-pass
filter.
March 1991
CVBS
SYNC
GND1
GND2
C
CSO
AD
SCL
SDA
RS
TP
DAV
R
CP
V
V
C
n.c.
SYMBOL
P
2
2
P1
P2
black
osc
ph
VPS dataline processor
C-bus not to acknowledge
C-bus transfer register to “FFF”
or, if external reset
PIN DESCRIPTION
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
video signal input (CVBS from TV)
sync amplitude input (CVBS from TV)
analog ground (0 V)
digital ground (0 V)
capacitor for black level
composite sync output
address set input
I
I
reset input active LOW
test point for line 16 decoder
data available output active LOW
oscillator resistor for frequency
adjustment
test point clock pulse
capacitor of phase detector
not connected
2
2
5 V supply voltage (digital part)
5 V supply voltage (analog part)
C-bus clock line
C-bus data line
P
.
To enable proper storage of the sync
value in the decoupling capacitor, the
sync generator output resistance
should not exceed 1 k .
Black level
The capacitor connected to pin 5
stores the black level value for the
adaptive sync slicer.
Composite sync output (CSO)
A composite sync output signal for
customer application is provided
(pin 6).
DAV output
The data available output pin 12 is set
LOW after an error free dataline 16 is
received. DAV returnes to HIGH after
the beginning of the next first field. If
4
PIN CONFIGURATION
handbook, halfpage
C black
SYNC
GND1
GND2
CVBS
CSO
SDA
SCL
AD
Fig.2 Pin configuration
no valid data is available DAV
remains HIGH. A short duration pulse
of 1 s (Fig.5) is inserted at the
beginning of dataline 16; it will ensure
that a HIGH-to-LOW transmission
occurs which can then be used for
triggering.
5 MHz VCO and phase detector
The resistor connected between pin
13 and V
into the voltage controlled oscillator.
The RC network connected to pin 17
acts as a low-pass filter for the phase
detector.
Power supply
To prevent crosscoupling the circuit is
provided with separate ground and
supply pins for analog and digital
parts (pins 3, 4, 15 and 16).
1
2
3
4
5
6
7
8
9
SAA4700
P2
MBH796
determines the current
Preliminary specification
18
17
16
15
14
13
12
11
10
n.c.
C ph
V P2
V P1
CP
R osc
DAV
TP
RS
SAA4700