k4s561633c-n Samsung Semiconductor, Inc., k4s561633c-n Datasheet - Page 8

• Manufacturer Part Number: k4s561633c-n
• Description: 16mx16 Sdram 54csp
• Manufacturer: Samsung Semiconductor, Inc.

K4S561633C-R(B)L/N/P
SIMPLIFIED TRUTH TABLE
Notes :
1. OP Code : Operand Code
2. MRS can be issued only at all banks precharge state.
3. Auto refresh functions are the same as CBR refresh of DRAM.
4. BA
5. During burst read or write with auto precharge, new read/write command can not be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
Register
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down Mode
DQM
No Operation Command
A
If both BA
If BA
If BA
If both BA
If A
New row active of the associated bank can be issued at t
A new command can be issued after 2 CLK cycles of MRS.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Another bank read/write command can be issued after the end of burst.
is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
0
~ A
0
10
~ BA
0
0
/AP is "High" at row precharge, BA
is "Low" and BA
is "High" and BA
12
& BA
1
0
0
: Bank select addresses.
and BA
and BA
COMMAND
0
~ BA
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
All Banks
1
1
are "Low" at read, write, row active and precharge, bank A is selected.
are "High" at read, write, row active and precharge, bank D is selected.
1
: Program keys. (@MRS)
1
1
is "High" at read, write, row active and precharge, bank B is selected.
is "Low" at read, write, row active and precharge, bank C is selected.
Entry
Entry
Entry
Exit
Exit
Exit
(V=Valid, X=Don t Care, H=Logic High, L=Logic Low)
0
and BA
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
L
L
L
1
are ignored and all banks are selected.
CKEn
X
H
H
X
X
X
X
X
H
H
X
L
L
L
RP
after the end of burst.
CS
H
H
H
H
H
L
L
L
L
L
L
L
L
L
X
L
L
L
RAS
X
H
H
H
H
H
H
L
L
X
L
L
X
V
X
X
X
V
X
CAS
H
H
H
H
H
H
L
L
X
L
L
X
V
X
X
X
V
X
WE
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
DQM
X
X
X
X
X
X
X
X
X
X
X
X
V
X
BA
V
V
V
V
X
0,1
CMOS SDRAM
Rev. 1.4 Dec. 2002
A
OP CODE
10
Row Address
H
H
H
L
L
L
/AP
X
X
X
X
X
X
X
A
A
Address
Address
Column
(A
Column
(A
11,
9
0
0
X
~ A
~ A
~ A
A
8
8
12,
)
)
0
Note
1, 2
4, 5
4, 5
3
3
3
3
4
4
6
7