k4s640432f Samsung Semiconductor, Inc., k4s640432f Datasheet - Page 3

• Manufacturer Part Number: k4s640432f
• Description: 4m X 4bit X 4 Banks Synchronous Dram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

4M x 4Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
FUNCTIONAL BLOCK DIAGRAM
K4S640432F
clock
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
ADD
CLK
LCKE
*
CLK
Samsung Electronics reserves the right to change products or specification without notice.
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
GENERAL DESCRIPTION
Latency & Burst Length
rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits,
fabricated with SAMSUNG s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
ORDERING INFORMATION
Programming Register
WE
K4S640432F-TC/L75
K4S640432F-TC/L1H
K4S640432F-TC/L1L
Data Input Register
The K4S640432F is 67,108,864 bits synchronous high data
Column Decoder
4M x 4
4M x 4
4M x 4
4M x 4
Part No.
DQM
LWCBR
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
Max Freq.
Rev.0.1 Sept. 2001
CMOS SDRAM
LDQM
Interface Package
LVTTL
LWE
LDQM
DQi
TSOP(II)
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