k4d28163hd Samsung Semiconductor, Inc., k4d28163hd Datasheet - Page 13

• Manufacturer Part Number: k4d28163hd
• Description: 128mbit Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

AC CHARACTERISTICS
case
CK cycle time
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
Clock half period
Data output hold time from DQS
Note 1 :
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
- tQHmin = tHP-X where
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst
variation and replaces tDV
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
strobe and all data associated with that data strobe are coincidentally valid.
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
K4D28163HD
Parameter
CL=3
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
CH
CL
DQSCK
AC
DQSQ
RPRE
RPST
DQSS
WPRES
WPREH
WPST
DQSH
DQSL
IS
I H
DS
DH
HP
Q H
Sym-
bol
tHP-0.4
tCLmin
tCHmin
Min
0.45
0.45
0.85
0.35
-0.6
-0.6
3.6
0.9
0.4
0.4
0.4
0.4
0.9
0.9
0.4
0.4
o r
0
-
-36
Max
0.55
0.55
1.15
0.6
0.6
0.4
1.1
0.6
0.6
0.6
0.6
6
-
-
-
-
-
-
-
-
tHP-0.4
tCHmin
tCLmin
Min
0.45
0.45
0.85
0.35
-0.6
-0.6
4.0
0.9
0.4
0.4
0.4
0.4
0.9
0.9
0.4
0.4
o r
0
-
-40
- 13 -
Max
0.55
0.55
1.15
0.6
0.6
0.4
1.1
0.6
0.6
0.6
0.6
7
-
-
-
-
-
-
-
-
tHP-0.45
tCHmin
tCLmin
Min
0.45
0.45
0.45
0.45
-0.7
-0.7
5.0
0.9
0.4
0.8
0.3
0.4
0.4
0.4
1.0
1.0
or
0
-
-50
Max
0.55
0.55
0.45
0.7
0.7
1.1
0.6
1.2
0.6
0.6
0.6
10
-
-
-
-
-
-
-
-
tCHmin
tHP-0.5
tCLmin
-0.75
-0.75
128M DDR SDRAM
Min
0.45
0.45
0.75
0.25
6.0
0.9
0.4
0.4
0.4
0.4
1.1
1.1
0.5
0.5
or
0
-
-60
Rev. 1.4(Aug. 2002)
Max
0.55
0.55
0.75
0.75
1.25
0.5
1.1
0.6
0.6
0.6
0.6
1 0
-
-
-
-
-
-
-
-
Unit Note
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1