k4t56043qf Samsung Semiconductor, Inc., k4t56043qf Datasheet - Page 32

• Manufacturer Part Number: k4t56043qf
• Description: 256mb F-die Ddr2 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

256Mb F-die DDR2 SDRAM
2. DDR2 SDRAM AC timing reference load
It is not intended to be either a precise representation of the typical system environment nor a depiction of the
actual load presented by a production tester. System designers will use IBIS or other simulation tools to cor-
relate the timing reference load to a system environment. Manufacturers will correlate to their production test
conditions (generally a coaxial transmission line terminated at the tester electronics).
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output tim-
ing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement
(e.g. DQS) signal.
3. DDR2 SDRAM output slew rate test load
4. Differential data strobe
“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM
pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling
edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data
strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm
Figure AA represents the timing reference load used in defining the relevant timing parameters of the part.
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or
Output slew rate is characterized under the test conditions as shown in Figure.
single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between
DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not
necessarily tested on each device.
between DQS and DQS for differential strobe.
VREF + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to
CK - CK = +500 mV
VDDQ
VDDQ
DUT
DUT
RDQS, RDQS
DQS, DQS
(250mV to -500 mV for falling egdes).
Figure AA : AC Timing Reference Load
Slew Rate Test Load
RDQS
RDQS
DQS
DQS
DQ
DQ
Output
Output
Test point
Timing
reference
point
Page 32 of 36
25
25
Ω
Ω
V
V
TT
TT
= V
= V
DDQ
DDQ
/2
/2
Rev. 0.91 (Sep. 2003)
DDR2 SDRAM
Preliminary