k4t51163qi-hpf7 Samsung Semiconductor, Inc., k4t51163qi-hpf7 Datasheet - Page 38

• Manufacturer Part Number: k4t51163qi-hpf7
• Description: 512mb I-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

20. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
21. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced from the differential data strobe crosspoint to the input signal crossing
22. Input waveform timing is referenced from the input signal crossing at the V
23. Input waveform timing is referenced from the input signal crossing at the V
K4T51163QI
under test. See Figure 19.
under test. See Figure 19.
data strobe crosspoint for a rising signal, and from the input signal crossing at the V
to the device under test. DQS, DQS signals must be monotonic between V
at the V
the device under test. DQS, DQS signals must be monotonic between V
IH
(DC) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the V
CK
CK
DQS
DQS
Figure 18 - Differential input waveform timing - tDS and tDH
Figure 19 - Differential input waveform timing - tIS and tIH
tIS
tDS
tIH
tDH
38 of 42
IL
(DC)max and V
IL
(DC)max and V
IH
IL
(DC) level for a rising signal and V
(AC) level for a rising signal and V
tDS
tIS
IL
(AC) level to the differential data strobe crosspoint for a falling signal applied
IH
(DC)min. See Figure 18.
tDH
IH
(DC)min. See Figure 18.
tIH
Industrial
V
V
V
V
V
V
V
IH
IL
DDQ
IH
IH
REF
IL
IL
SS
V
V
V
V
V
V
V
(DC)max
(AC)max
(AC) for a falling signal applied to the device
(DC) for a falling signal applied to the device
(AC)min
(DC)min
DDQ
IH
IH
REF
IL
IL
SS
(DC)
(DC)max
(AC)max
(AC)min
(DC)min
IL
(DC)
(DC) level for a rising signal applied to
Rev. 1.0 August 2009
DDR2 SDRAM
IH
(AC) level to the differential