k4t51043qe-zlcc Samsung Semiconductor, Inc., k4t51043qe-zlcc Datasheet - Page 43

• Manufacturer Part Number: k4t51043qe-zlcc
• Description: 512mb E-die Ddr2 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

Definitions :
- tCK(avg)
- tCH(avg) and tCL(avg)
- tJIT(duty)
- tJIT(per), tJIT(per,lck)
- tJIT(cc), tJIT(cc,lck)
- tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per)
K4T51043QE
K4T51083QE
K4T51163QE
tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter is the larg-
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).
tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing.
tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles : tJIT(cc) = Max of |tCK
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing.
tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg).
tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)}
where,
tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200}
tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200}
est deviation of any single tCL from tCL(avg).
tCK(avg) =
tCH(avg) =
tCL(avg) =
where
where
where
∑
∑
∑
j = 1
j = 1
j = 1
N
N
N
N = 200
N = 200
N = 200
tCK
tCH
tCL
j
j
j
where
/N
/(N x tCK(avg))
/(N x tCK(avg))
tERR(nper) =
n = 2
n = 3
n = 4
n = 5
6 ≤ n ≤ 10
11 ≤ n ≤ 50
∑
j = 1
i + n - 1
43 of 45
tCK
for
for
for
for
for
for
j
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6-10per)
tERR(11-50per)
- n x tCK(avg)
i+1
- tCKi|
DDR2 SDRAM
Rev. 1.8 July 2007