k4t51043qb-zcd5 Samsung Semiconductor, Inc., k4t51043qb-zcd5 Datasheet
k4t51043qb-zcd5
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k4t51043qb-zcd5 Summary of contents
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... B-die DDR2 SDRAM 512Mb B-die DDR2 SDRAM Specification INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... B-die DDR2 SDRAM Contents 0. Ordering Information 1. Key Feature 2. Package Pinout/Mechanical Dimension & Addressing 2.1 Package Pinout & Mechanical Dimension 2.2 Input/Output Function Description 2.3 Addressing 3. Absolute Maximum Rating 4. AC & DC Operating Conditions & Specifications Page DDR2 SDRAM Rev. 1.5 July 2005 ...
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... B-die DDR2 SDRAM 0. Ordering Information Organization DDR2-533 4-4-4 K4T51043QB-GCD5 128Mx4 K4T51043QB-ZCD5 K4T51083QB-GCD5 64Mx8 K4T51083QB-ZCD5 K4T51163QB-GCD5 32Mx16 K4T51163QB-ZCD5 Note : Speed bin is in order of CL-tRCD-tRP. 1.Key Features Speed CAS Latency tRCD(min) tRP(min) tRC(min) • JEDEC standard 1.8V ± 0.1V Power Supply • VDDQ = 1.8V ± 0.1V • 200 MHz f ...
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... B-die DDR2 SDRAM 2. Package Pinout/Mechanical Dimension & Addressing 2.1 Package Pinout x4 package pinout (Top View) : 60ball FBGA Package 1 VDD NC VDDQ NC VDDL NC VSS VDD Notes: 1. Pin B3 has identical capacitance as pin B7. 2. VDDL and VSSDL are power and ground for the DLL. Ball Locations (x4) ...
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... B-die DDR2 SDRAM x8 package pinout (Top View) : 60ball FBGA Package 1 VDD DQ6 VDDQ DQ4 VDDL NC VSS VDD Notes: 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & ...
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... B-die DDR2 SDRAM x16 package pinout (Top View) : 84ball FBGA Package 1 VDD UDQ6 VSSQ VDDQ UDQ1 UDQ4 VSSQ VDD LDQ6 VSSQ VDDQ LDQ4 VSSQ VDDL NC VSS VDD Note : 1. VDDL and VSSDL are power and ground for the DLL case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used. ...
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... B-die DDR2 SDRAM FBGA Package Dimension(x4/x8 60- 0.45r ‡ 0.05 ‡0.2 #A1 11. INDEX MARK 6.40 0.80 1. ...
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... B-die DDR2 SDRAM FBGA Package Dimension(x16 84- 0.45r ‡ 0.05 ‡0.2 #A1 11. INDEX MARK 6.40 0.80 1. ...
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... Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on CS Input systems with multiple Ranks considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For ODT Input x16 configuration, ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal ...
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... B-die DDR2 SDRAM 2.3 512Mb Addressing Configuration # of Bank Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 256Mb Configuration # of Bank Bank Address Auto precharge Row Address Column Address 1Gb Configuration ...
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... Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. ...
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... Parameter TOPER Operating Temperature 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3 required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate. ...
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... B-die DDR2 SDRAM Differential input AC logic Level Symbol Parameter V ID(AC) AC differential input voltage V IX(AC) AC differential cross point voltage Notes (AC) specifies the input differential voltage |V ID and V is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal ...
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... The absolute value of the slew rate as measured from equal to or greater than the slew rate as measured from AC to AC. This is guaran- teed by design and characterization. 6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty. Output slew rate load : 7 ...
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... B-die DDR2 SDRAM IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; ...
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... B-die DDR2 SDRAM For purposes of IDD testing, the following parameters are utilized Parameter CL(IDD) t RCD(IDD) t RC(IDD) t RRD(IDD)-x4/x8 t RRD(IDD)-x16 t CK(IDD) t RASmin(IDD) t RP(IDD) t RFC(IDD) Detailed IDD7 The detailed timings are shown below for IDD7. Legend Active Read with Autoprecharge Deselect IDD7: Operating Current: All Bank Interleave Read operation All banks are being interleaved at minimum t RC(IDD) without violating t RRD(IDD) and t FAW(IDD) using a burst length of 4 ...
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... IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 Normal IDD7 Symbol D5(DDR2-533@CL=4) IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 Normal IDD7 128Mx4(K4T51043QB) CC(DDR2-400@CL=3) 100 95 110 100 175 130 170 140 195 185 5 ...
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... B-die DDR2 SDRAM Input/Output capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Electrical Characteristics & AC Timing for DDR2-533/400 (0 qC < ...
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... B-die DDR2 SDRAM Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input hold time DQ and DM input setup time Control & ...
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... B-die DDR2 SDRAM Parameter CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency ...
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... The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig- nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown in the following figure ...
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... DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent ...
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... B-die DDR2 SDRAM Specific Notes for dedicated AC parameters 9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing. ...
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... B-die DDR2 SDRAM 18. tIS and tIH (input setup and hold) derating. 2.0 V/ns 'tIS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 0.9 -11 Command/ Address Slew 0.8 -25 rate(V/ns) 0.7 -43 0.6 -67 0.5 -110 0.4 -175 0.3 -285 0.25 -350 0.2 -525 0.15 -800 2.0 V/ns 'tIS 4.0 +150 3.5 +143 3.0 +133 2.5 +120 2.0 +100 1.5 +67 1.0 0 0.9 -5 Command/ 0.8 -13 Address Slew 0.7 -22 rate(V/ns) ...
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... B-die DDR2 SDRAM 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH) ...
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... B-die DDR2 SDRAM tHZ tRPST end point T1 tHZ,tRPST end point = 2*T1-T2 29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V tial data strobe crosspoint for a rising signal, and from the input signal crossing at the V nal applied to the device under test ...
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... B-die DDR2 SDRAM 31. Input waveform timing is referenced from the input signal crossing at the V device under test. 32. Input waveform timing is referenced from the input signal crossing at the V device under test 33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency. 34. Input waveform timing with single-ended data strobe enabled MR[bit10 referenced from the input signal crossing at the VIH(ac) level to the sin- gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single- ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test ...
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... Initial Release Version 1.1 (Jun. 2004) - Added Lead-Free part number in ordering information. - Changed IDD2P - Corrected Typo Version 1.2 (Jan. 2005) - Removed DDR2-667 SDRAM at this datasheet - Revised current test AC spec condition - Added derating table Version 1.3 (Jan. 2005) - Corrected typo Version 1.4 (Feb. 2005) - Corrected from 6.15mm to 5.5mm in dimension of x16 PKG Version 1 ...