k4t1g084qa-zce60 Samsung Semiconductor, Inc., k4t1g084qa-zce60 Datasheet - Page 19

• Manufacturer Part Number: k4t1g084qa-zce60
• Description: 1gb A-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
1G A-die DDR2 SDRAM
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for each input tIPW
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals tDQSQ
DQ hold skew factor
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock
edge
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Active to active command period for 1KB page size
products
Active to active command period for 2KB page size
products
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
Parameter
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH(base)
tDS(base)
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
tRRD
tRRD
tFAW
tFAW
Symbol
min(tCL, tCH)
tHP - tQHS
2*tAC min
tAC min
3000
-0.25
min
-400
0.45
0.45
0.35
0.35
0.35
37.5
-450
175
100
0.35
275
200
0.6
0.2
0.2
0.4
0.9
0.4
7.5
10
50
x
2
x
x
DDR2-667
Page 19 of 28
tAC max
tAC max
tAC max
max
+400
8000
0.55
0.55
0.25
+450
240
0.6
1.1
0.6
340
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
min(tCL, tCH)
tHP - tQHS
2* tACmin
tAC min
3750
-0.25
min
0.45
0.45
0.35
0.35
37.5
-500
-450
225
100
0.35
375
250
0.6
0.2
0.2
0.4
0.35
0.9
0.4
7.5
10
50
2
x
x
x
DDR2-533
tAC max
tAC max
tAC max
max
+500
+450
8000
0.55
0.55
0.25
300
400
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
min(tCL, tCH)
tHP - tQHS
2* tACmin
tAC min
5000
-0.25
min
-600
-500
0.45
0.45
0.35
0.35
0.35
37.5
275
150
0.35
475
350
0.6
0.2
0.2
0.4
0.9
0.4
7.5
10
50
x
2
x
x
DDR2-400
DDR2 SDRAM
Rev. 1.1 Aug. 2005
tAC max
tAC max
tAC max
max
+600
+500
0.55
0.55
8000
0.25
350
450
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Units Notes
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
15,16,
15,16,
14,16,
14,16,
20,21
17,20
17,21
18,23
18,22
24
27
27
22
21
19
28
28
12
12