at52bc6402a ATMEL Corporation, at52bc6402a Datasheet
at52bc6402a
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at52bc6402a Summary of contents
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... V Operation CC • Access Time Stack Module Description The AT52BC6402A(T) consists of a 64-Mbit Flash stacked with a 16-Mbit PSRAM in a single CBGA package. Stack Module Memory Contents Device Memory Combination AT52BC6402A(T) 64M Flash + 16M PSRAM Flash/PSRAM Read Access ...
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... CBGA 66C4 – Top View Pin Configurations AT52BC6402A( A20 A11 A15 B A16 A8 A10 C WE A21 D PSGND RESET E WP VPP A19 PSOE G A18 A17 Pin Name Function A0 - A21 Address I/O0 - I/O15 Data Inputs/Outputs CE1 Flash Chip Enable ...
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Flash Description Device Operation 3441B–STKD–11/04 The 64-Mbit Flash memory is divided into multiple sectors and planes for erase opera- tions. The devices can be read or reprogrammed off a single 2.7V power supply, making them ideally suited for in-system ...
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... AT52BC6402A(T) 4 ERASE: Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical “1”. The entire memory can be erased by using the Chip Erase command or individual planes or sectors can be erased by using the Plane Erase or Sector Erase commands. CHIP ERASE: Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse ...
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Table 1. Hardlock and Softlock Protection Configurations in Conjunction with WP Hard- Soft lock lock ...
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... AT52BC6402A(T) 6 SECTOR PROTECTION DETECTION: A software method is available to determine if the sector protection Softlock or Hardlock features are enabled. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from the I/O0 and I/O1 at address location 00002H within a sector will show if the sector is unlocked, softlocked, or hardlocked ...
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Examining the toggle bit may begin at any time during a pro- gram cycle. Please see Table 3 on page 11 for more details. The toggle bit status bit should be used in ...
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... AT52BC6402A(T) 8 128-BIT PROTECTION REGISTER: The 64-Mbit device contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. ...
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Figure 2. Data Polling Algorithm (Configuration Register = 00) START Read I/O7 - I/O0 Addr = VA YES I/O7 = Data I/O3, I/ YES Read I/O7 - I/O0 Addr = VA I/O7 = Data? NO Program/Erase ...
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... Program/Erase Operation Not Successful, Write Product ID Exit Command Note: 1. The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop toggling as I/O5 changes to “1”. AT52BC6402A(T) 10 Figure 5. Toggle Bit Algorithm (Configuration Register = 01) NO Program/Erase Operation Successful, Device in ...
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Table 3. Status Bit Table I/O7 Configuration Register: 00/01 00/01 00/01 Read Address Plane A Plane B Plane C In While Programming I/O7/0 DATA DATA in Plane A Programming DATA I/O7/0 DATA in Plane B Programming DATA DATA I/O7/0 in ...
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... Any address within the user programmable register region. Please see “Protection Register Addressing Table” on page 13. 12. For the AT49BV6416, xxxx = 0000H. For the AT49BV6416T, xxxx = 3F80H. 13. For the AT49BV6416, xxxx = 0000H. For the AT49BV6416T, xxxx = 0F80H. AT52BC6402A(T) 12 (1) 1st Bus ...
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Absolute Maximum Ratings* Temperature under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages Except V PP (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V V Input Voltage PP with Respect to Ground ...
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... SA38 32K B SA39 32K B SA40 32K B SA41 32K B SA42 32K B SA43 32K B SA44 32K AT52BC6402A(T) 14 Memory Organization – 64-Mbit Bottom Boot (Continued) x16 Address Range Plane (A21 - A0) B 00000 - 00FFF B 01000 - 01FFF B 02000 - 02FFF B 03000 - 03FFF B 04000 - 04FFF B 05000 - 05FFF B 06000 - 06FFF ...
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Memory Organization – 64-Mbit Bottom Boot (Continued) Size Plane Sector (Words) C SA90 32K C SA91 32K C SA92 32K C SA93 32K C SA94 32K C SA95 32K C SA96 32K C SA97 32K C SA98 32K C SA99 ...
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... SA38 32K C SA39 32K C SA40 32K C SA41 32K C SA42 32K C SA43 32K C SA44 32K AT52BC6402A(T) 16 Memory Organization – 64-Mbit Top Boot (Continued) x16 Address Range Plane (A21 - A0) C 00000 - 07FFF C 08000 - 0FFFF C 10000 - 17FFF C 18000 - 1FFFF C 20000 - 27FFF C 28000 - 2FFFF C 30000 - 37FFF ...
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Memory Organization – 64-Mbit Top Boot (Continued) Size Plane Sector (Words) B SA90 32K B SA91 32K B SA92 32K B SA93 32K B SA94 32K B SA95 32K A SA96 32K A SA97 32K A SA98 32K A SA99 ...
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... X can Refer to AC programming waveforms. 3. Manufacturer Code: 001FH; Device Code: 00D6H – Bottom Boot; 00D2H – Top Boot. 4. The VPP pin can be tied (min) = 1.65V. IHPP 6. V (max) = 0.8V. ILPP AT52BC6402A(T) 18 Industrial (4) WE RESET ...
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DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CMOS SB1 CC ( Active Current Read While Erase Current CCRE Read While ...
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... DF t RESET to Output Delay RO Asynchronous Read Cycle Waveform Notes may be delayed may be delayed without impact ACC specified from OE or CE, whichever occurs first ( pF). DF AT52BC6402A(T) 20 64-Mbit-70 Min Max 150 (1)(2)(3) tRC A0 - A21 ADDRESS VALID ...
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AC Word Load Characteristics Symbol Parameter t Address Setup Time to WE and CE Low AS t Address Hold Time AH t Data Setup Time DS t Data Hold Time Low Pulse Width WP t ...
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... Command Definitions on page 12.) 3. For chip erase, the data should be XX10H, for plane erase, the data should be XX20H, and for sector erase, the data should be XX30H 4. The waveforms shown above use the WE controlled AC Word Load Waveforms. AT52BC6402A( ...
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Data Polling Characteristics Symbol Parameter t Data Hold Time Hold Time OEH Output Delay OE t Write Recovery Time WR Notes: 1. These parameters are characterized and not 100% tested. 2. See t spec ...
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... AT52BC6402A(T) 24 Comments “Q” “R” “Y” VCC min write/erase VCC max write/erase VPP min voltage VPP max voltage Typ word write – 16 µs Typ block erase – 500 ms ...
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Table 4. Common Flash Interface Definition for 64-Mbit Device (Continued) Address 64-Mbit Device 41h 0050h 42h 0052h 43h 0049h 44h 0031h 45h 0030h 46h 008Fh 47h 0000h Top Boot or 0001h Bottom Boot 48h 0000h 49h 0000h 4Ah 0080h 4Bh ...
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... PSRAM Description Features Block Diagram AT52BC6402A(T) 26 The device is a 16-Mbit 1T/1C PSRAM featured by high-speed operation and super low power consumption. The 16-Mbit device adopts one transistor memory cell and is orga- nized as 1,048,576 words by 16 bits. It operates in the extended range of temperatures and supports a wide operating voltage range. The device also supports the deep power- down mode for a super low standby current. • ...
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Absolute Maximum Ratings Symbol Parameter Input/Output Voltage IN OUT V Power Supply CC T Ambient Temperature A T Storage Temperature STG P Power Dissipation D T Ball Soldering Temperature and Time SOLDER Note: 1. Stresses greater than ...
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... OH (1) Capacitance (Temp = 25° 1.0 MHz) Symbol Parameter C Input Capacitance (Add, CS1, CS2, IN PSWE, PSOE, UB, LB) C Output Capacitance (I/O) OUT Note: 1. These parameters are sampled and not 100% tested. AT52BC6402A(T) 28 Test Condition GND < V < GND < V < OUT CC CS1 = V , CS2 = ...
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AC Characteristics V = 2.7V ~ 3.1V -30°C to 85°C (I), Unless Otherwise Specified Symbol Parameter Read Cycle 1 t Read Cycle Time Address Access Time Chip Select Access ...
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... AC Test Loads Power-up Sequence Deep Power-down Entry Sequence Deep Power-down Exit Sequence State Diagram AT52BC6402A( OUT Ohm 0 Note: Including jig and scope capacitance. 1. Supply power. 2. Maintain stable power for longer than 200 µs. 1. Keep CS2 low state. Deep Power-down mode is maintained while CS2 is low state ...
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Timing Diagrams Power-up Sequence Timing V CC CS2 CS1 Note: Power-up time is defined when CS2 is kept high before V low level to high level, after V Deep Power-down Entry/Exit Sequence Timing Suspend 1 µs CS2 CS1 Note: When ...
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... CHZ BHZ OHZ are defined as the time at which the outputs achieve the low impedance state. These are not referenced to output voltage levels. 4. CS1 in high for the standby, low for active. AT52BC6402A( ...
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Write Cycle 1 (PSWE Controlled) ADDRESS CS1 CS2 V IH UB,LB PSWE HIGH-Z DATA IN DATA OUT Write Cycle 2 (CS1 Controlled) ADDRESS CS1 CS2 V IH UB, LB PSWE HIGH-Z DATA IN HIGH-Z DATA OUT Notes write ...
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... ADDRESS CS1 CS2 V IH UB, LB PSWE HIGH-Z DATA IN Notes: 1. The t is specified from the time satisfied both Although UB and LB are high state, it’s illegal function to change address both CS and PSWE are in low state. AT52BC6402A( ...
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Avoid Timing Abnormal Timing CS1 PSWE ADDRESS Avoidable Timing (1) CS1 PSWE ADDRESS Avoidable Timing (2) CS1 PSWE ADDRESS 3441B–STKD–11/04 The 16-Mbit PSRAM has a timing which is not supported at read operation. If your sys- tem has multiple invalid ...
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... Ordering Information t ACC (ns) Ordering Code AT52BC6402A-70CI 70 AT52BC6402AT-70CI AT52BC6402A-85CI 85 AT52BC6402AT-85CI 66C6 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA) AT52BC6402A(T) 36 Flash Boot Block PSRAM Bottom Top Bottom Top Package Type Package Operation Range Industrial 66C6 (-40° to 85°C) ...
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Packaging Information 66C6 – CBGA Marked A1 Identifier E 1.10 REF Bottom View 2325 Orchard Parkway San Jose, CA 95131 R 3441B–STKD–11/04 D Top View D1 ...
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... Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2004. All rights reserved. Atmel are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...