hip0063 Intersil Corporation, hip0063 Datasheet - Page 6

• Manufacturer Part Number: hip0063
• Description: Hex Low Side Mosfet Driver With Serial Or Parallel Interface And Diagnostic Fault Control
• Manufacturer: Intersil Corporation

Applications
Input Control
The application circuit for the HIP0063 is shown in Figure 1
while details of input control are shown in the block diagram.
Gate control and diagnostic fault management are provided
for each of six channels. Gate controlled switching is OR’d by
the SPI Bus microcontroller interface or the independent par-
allel logic inputs (PI0-1) as a user option. The six control
channels provide gate drive (G0-5) for the MOS output drivers
while detecting fault conditions at each output via the drain
monitor pins (D0-5). An HLOS input control overrides the
serial input and modifies the parallel operation.
SI (serial input) data from a SPI controller is clocked into the
input register on the positive leading edge of the clock pulse,
SCK while CS is low. (Data is clocked from the SO output on
the trailing edge of the SCK clock pulse.) Either 8-bit or 16-bit
control may be used. The input data is clocked MSB first and
all unused bits should be low. Detailed information on the bit
structure for both 8-bit and 16-bit operation is shown in Table 1.
A special feature of the HIP0063 is a PWM mode of operation
set by a high on the HLOS pin. This mode is primarily used to
control fuel injectors and allows direct access to control chan-
nels 0 and 1 from the HPW01 Pin and channels 4 and 5 from
the HPW45 Pin. When HLOS is high, the serial input is dis-
abled and SO goes to three-state. Channel#2 and Channel#3
are independently controlled from the parallel input during the
HLOS/PWM operation. A pullup is needed on the SO pin to
keep the SO output high when HLOS/PWM is active.
Fault Protection
Output fault conditions are monitored at the Drain Monitor pin, DO.
Feed back of the fault condition is returned by the SPI SO data out-
put when new data is clocked by SCK into the SI data input.
Output Load Short conditions are detected at the drain moni-
tor pin when the Output is ON and the drain voltage is greater
than the specified V
greater than t
8-BIT MODE:
16-BIT MODE:
MSB
MSB
Bits 0 to 5:
Bit 6:
Bit 7:
Note:
Bits 0 to 5:
Bit 6:
Bit 7:
Bits 8 to 13: Fault bits for outputs 0 to 5 respectively. Returned as sent or returned as the complement to indicate an output fault.
Bit 14:
Bit 15:
15
7
14
6
SC_ON
Turns-ON the corresponding output gate when set HIGH.
Not used, set LOW (Reserved as a test bit).
Bit 7 can be used as an HLOS flag. Always set LOW. If the complement is returned, then HLOS is active.
(i.e., HLOS forces SO into a three-state mode and a HIGH will be returned)
Fault Bits clocked out when data clocked in.
Turn-ON the corresponding channel output gate when set HIGH and will always be returned as sent.
Not used, set LOW. (Reserved as a test bit).
Not used, (Will be returned as sent).
Not used, (Will be returned as sent).
HLOS bit, (See bit 7 for the 8-bit mode).
13
. When the output load short is detected,
5
DM_FTH
TABLE 1. SPI DATA FORMAT - BIT DEFINITION FOR DATA INPUT AND OUTPUT
12
4
voltage threshold for a time
11
3
10
2
1
9
HIP0063
LSB
0
8
6
the output goes to a low duty cycle mode. The duty cycle is a
ratio of the ON time required to sense and enter the low duty
cycle mode (t
t
Open Load fault conditions are detected when the Output is
OFF and the drain voltage falls below the V
level for a time greater than t
Open Load faults will not be detected.
For Load Short and Open Load fault conditions, a fault bit with
a logic state of “1” is placed in the respective fault register. If
the fault is terminated, the bit returns to “0”. When CS goes
low for serial communication, all fault bits are latched. Fault
data is read at SO when CS is low and SCK is clocked. When
CS goes high, new data may enter the fault register.
The V
over-voltage fault conditions. Over-voltage protection shuts
down all output drivers when the over-voltage threshold of typ-
ically 35V is detected at the V
or off, V
put gates.
Each output of the HIP0063 has a drain-to-gate zener diode
clamp to limit peak voltage at the drain of the output drivers.
The voltage pulse from switched inductive loads is clamped
when the drain-to-gate zener forces the output driver into con-
duction. The MOSFET drain-to-source output clamp voltage
level is typically 67V.
Diagnostic Feedback
Normal operation in the SPI mode calls for bits 0 thru 5 to be sent
as a “1” to control turn-on. Bit 6 is always low (reserved for use as
a test bit) and bit 7 should be low to provide a flag for HLOS/
PWM operation. When there is no fault condition, the return bits
from SO will be the same as the bits sent. Fault conditions return
the XOR complement. When the complement is received, it may
also indicate an error in communication or HLOS/PWM con-
trolled operation has occurred. A CPU instruction to send the last
command will verify HLOS action. After the HLOS action is termi-
nated, resending the previous command will verify normal opera-
SC_REF.
7
PWR
PWR
6
pin monitors the supply voltage (battery supply) for
supplies the necessary bias to switch off all out-
SC_ON
5
.
) and the following refresh OFF time,
4
PWR
OL_OFF
3
pin. If the V
. If the Output is ON,
2
DM_FTH
CC
1
supply is low
threshold
LSB
0