scn68652ac2n40 NXP Semiconductors, scn68652ac2n40 Datasheet - Page 15

• Manufacturer Part Number: scn68652ac2n40
• Description: Scn2652/scn68652 Multi-protocol Communications Controller Mpcc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 8.
DC ELECTRICAL CHARACTERISTICS
1995 May 1
Multi-protocol communications controller (MPCC)
PARAMETER
PARAMETER
Input voltage
V
V
Output voltage
V
V
I
Leakage current
I
I
Capacitance
C
C
00–07
12–14
CC
IL
OL
IL
IH
OL
OH
IN
OUT
BIT
08
09
10
11
15
Low
High
Low
High
Power supply current
Input
Output
Input
Output
Receiver Data/Status Register (RDSR)–(Read Only)
RAB/GA
NAME
RSOM
REOM
RERR
RxDB
ROR
ABC
BOP/BCP
BOP/BCP
BOP/BCP
MODE
BOP
BOP
BOP
BOP
FUNCTION
Receiver data buffer. Contains assembled characters from the RxSR. If VRC is specified, the
parity bit is stripped.
Receiver start of message = 1 when a FLAG followed by a non-FLAG has been received and
the latter character matches the secondary station if SAM = 1. RxA will be asserted when
RSOM = 1. RSOM resets itself after one character time and has no affect on RxSA.
Receiver end of message = 1 when the closing FLAG is detected and the last data character
is loaded into RxDB or when an ABORT/GA character is received. REOM is cleared on
reading RDSR
Received ABORT or GA character = 1 when the receiver senses an ABORT character if
SS/GA = 0 or a GA character if SS/GA = 1. RAB/GA is cleared on reading RDSR
operation, or dropping of RxE. A received abort does not set RxDA.
Receiver overrun = 1 indicates the processor has not read last character in the RxDB within
one character time + 1/2 RxC period after RxDA is asserted. Subsequent characters will be
lost. ROR is cleared on reading RDSR
Assembled bit count. Specifies the number of bits in the last received data character of a
message and should be examined by the processor when REOM = 1(RxDA and RxSA
asserted). ABC = 0 indicates the message was terminated (by a flag or GA) on a character
boundary as specified by PCR
character. ABC is cleared when RDSR
residual character is right justified inRDSR
Receiver error indicator should be examined by the processor when REOm = 1 in BOP, or
when the processor determines the last data character of the message in BCP with CRC or
when RxSA is set in BCP with VRC.
CRC–CCITT preset to 1’s/0’s as specified by PCSAR
CRC–16 preset to 0’s on 8-bit characters specified by PSCAR
VRC specified by PCSAR
1, 2
RERR = 1 indicates FCS error (CRC
RERR = 0 indicates FCS received correctly (CRC = F0B8 or = 0)
RERR = 1 indicates CRC–16 received correctly (CRC = 0).
RERR = 0 indicates CRC–16 error (CRC 0)
RERR = 1 indicates VRC error
RERR = 0 indicates VRC is correct.
V
V
TEST CONDITIONS
TEST CONDITIONS
CC
V
V
OUT
V
IN
OUT
I
IN
= 5.25V, T
OH
I
OL
= 0V, f = 1MHz
= 0V, f = 1MHz
= 0 to 5.25V
H
= 0 to 5.25V
= –100 A
= 1.6mA
, reset operation, or dropping of RxE.
A
15
= 0 C
8–10
:
8–10
. Otherwise, ABC = number of bits in the last data
H
H
, reset operation, or dropping of RxE.
is read, reset operation, or dropping RxE. The
F0B8 or
L
.
Min
2.0
2.4
0)
8–10
SCN2652/SCN68652
:
LIMITS
Typ
8–10
:
Max
150
0.8
0.4
10
10
20
20
Product specification
H
, reset
UNIT
UNIT
mA
pF
V
V
A