am85c30 Advanced Micro Devices, am85c30 Datasheet - Page 18

• Manufacturer Part Number: am85c30
• Description: Enhanced Serial Communications Controller
• Manufacturer: Advanced Micro Devices

Read Registers
The ESCC contains eight Read registers [actually nine,
counting the receive buffer (RR8) in each channel]. Four
of these may be read to obtain status information (RR0,
RR1, RR10, and RR15). Two registers (RR12 and
RR13) may be read to learn the baud rate generator
time constant. RR2 contains either the unmodified inter-
rupt vector (Channel A) or the vector modified by status
information (Channel B). RR3 contains the Interrupt
Pending (IP) bits (Channel A). In addition, if bit D
WR15 is set, RR6 and RR7 are available for providing
frame status from the 10
Figure 8 shows the formats for each Read register.
The status bits of RR0 and RR1 are carefully grouped to
simplify status monitoring, for example, when the inter-
rupt vector indicates a Special Receive Condition
interrupt, all the appropriate error bits can be
read from a single register (RR1). Please refer to
18
AMD
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
D/C
Code In WR0:
“Point High”
Either Way
Not True
Not True
Not True
Not True
Not True
Not True
Not True
Not True
True
True
True
True
True
True
True
True
19 bit Frame Status FIFO.
Table 2. Register Addressing
2
Am85C30
of
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Am85C30 Technical Manual for detailed descriptions of
the read registers.
Write Registers
The ESCC contains 15 Write registers (16 counting
WR8, the transmit buffer) in each channel. These Write
registers are programmed separately to configure the
functional “personality” of the channels. Two registers
(WR2 and WR9) are shared by the two channels that
can be accessed through either of them. WR2 contains
the interrupt vector for both channels, while WR9 con-
tains the interrupt control bits. In addition, if bit D
WR15 is set, Write Register 7 prime (WR7 ) is available
for programming additional SDLC/HDLC enhance-
ments. When bit D
WR7 actually writes to WR7 to further enhance the
functional “personality” of each channel. Figure 8 shows
the format of each Write register.
D
In WR0:
2
, D
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
, D
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
of WR15 is set, executing a write to
Register
Write
Data
Data
10
11
12
13
14
15
0
1
2
3
4
5
6
7
9
Register
Read
Data
Data
(15)
(10)
(0)
(1)
(2)
(3)
10
12
13
15
0
1
2
3
–
0
of